From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dns1.vpop.net ([216.193.240.2] helo=mail.vpop.net) by pentafluge.infradead.org with esmtp (Exim 4.63 #1 (Red Hat Linux)) id 1Iify8-0007wL-HW for linux-mtd@lists.infradead.org; Fri, 19 Oct 2007 01:44:07 +0100 From: Matt Reimer To: linux-mtd@lists.infradead.org Subject: [PATCH] MTD: add s3c2440-specific read_buf/write_buf Date: Thu, 18 Oct 2007 17:43:07 -0700 Message-Id: <1192754587-25256-1-git-send-email-mattjreimer@gmail.com> Cc: Matt Reimer List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Matt Reimer Add read_buf/write_buf for s3c2440, which can read/write 32 bits at a time rather than just 8. In my testing on an s3c2440a running at 400 MHz with a 100 MHz HCLK, read performance improves by 36% (from 5.19 MB/s to 7.07 MB/s). Signed-off-by: Matt Reimer --- drivers/mtd/nand/s3c2410.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 5fac4c4..903db18 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -488,12 +488,24 @@ static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) readsb(this->IO_ADDR_R, buf, len); } +static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); + readsl(info->regs + S3C2440_NFDATA, buf, len / 4); +} + static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { struct nand_chip *this = mtd->priv; writesb(this->IO_ADDR_W, buf, len); } +static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); + writesl(info->regs + S3C2440_NFDATA, buf, len / 4); +} + /* device management functions */ static int s3c2410_nand_remove(struct platform_device *pdev) @@ -604,6 +616,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, info->sel_bit = S3C2440_NFCONT_nFCE; chip->cmd_ctrl = s3c2440_nand_hwcontrol; chip->dev_ready = s3c2440_nand_devready; + chip->read_buf = s3c2440_nand_read_buf; + chip->write_buf = s3c2440_nand_write_buf; break; case TYPE_S3C2412: -- 1.5.3.2