Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

[Rick van Rein]

Hello,

Thanks a lot for the detailed FAQ + documentation on the Linux MTD
subsystem.  It brought me from a novice on the Linux implementation
to someone who feels in control.

I am working to get a modest Linux distro going on what originally was
a 7 Watt thin client running Win XPe.  Since IDE is amazingly slow (it
consumes 80% CPU time in IRQ handlers) I wanted to try direct access
through JFFS2 to the NAND chips.

Processor:	Geode GX
Chipset:	Geode CS5535
NAND flash:	Toshiba TC58DVM92A1FT00 (512 MB x8, a 3 to 5 of them)
Controller:	If there's a CompactFlash ctlr it is concealed from me
Linux kernel:	2.6.31.6 without IDE but with CS553x NAND and JFFS2

When I boot this setup (over PXE), it reports:

CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

Tracing this back in the code, this refers to an either-IDE-or-flash
setting in the MSR that was either setup by RESET or the BIOS.  The
hardware works like that, the pins for IDE and NAND flash are multiplexed.
I am not sure in XPe would see this, so if this flag is meaningful...?

What surprised me was that the kernel contained no ways of setting this
value to inform the NAND driver that it can play freely; is this because
the hardware is wired purely for IDE operation?  Or does the slow IDE
responsiveness indicate that it is in fact flash, but not properly setup?

Is there a proper way of setting this flag without patching the kernel?


Thanks for any help you care to give,


Cheers,

Rick van Rein
GroenGemak
http://groengemak.nl/en/

Re: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

[David Woodhouse]

On Mon, 2009-11-30 at 08:40 +0000, Rick van Rein wrote:
> Hello,
> 
> Thanks a lot for the detailed FAQ + documentation on the Linux MTD
> subsystem.  It brought me from a novice on the Linux implementation
> to someone who feels in control.
> 
> I am working to get a modest Linux distro going on what originally was
> a 7 Watt thin client running Win XPe.  Since IDE is amazingly slow (it
> consumes 80% CPU time in IRQ handlers) I wanted to try direct access
> through JFFS2 to the NAND chips.
> 
> Processor:	Geode GX
> Chipset:	Geode CS5535
> NAND flash:	Toshiba TC58DVM92A1FT00 (512 MB x8, a 3 to 5 of them)
> Controller:	If there's a CompactFlash ctlr it is concealed from me
> Linux kernel:	2.6.31.6 without IDE but with CS553x NAND and JFFS2
> 
> When I boot this setup (over PXE), it reports:
> 
> CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS
> 
> Tracing this back in the code, this refers to an either-IDE-or-flash
> setting in the MSR that was either setup by RESET or the BIOS.  The
> hardware works like that, the pins for IDE and NAND flash are multiplexed.
> I am not sure in XPe would see this, so if this flag is meaningful...?
> 
> What surprised me was that the kernel contained no ways of setting this
> value to inform the NAND driver that it can play freely; is this because
> the hardware is wired purely for IDE operation?  Or does the slow IDE
> responsiveness indicate that it is in fact flash, but not properly setup?
> 
> Is there a proper way of setting this flag without patching the kernel?

If you have the NAND hardware connected, then surely your firmware ought
to be setting the MSRs appropriately?

See http://david.woodhou.se/olpc-enable-nand.c for an example of how to
make it work if your firmware doesn't, though.

Of course, we didn't need that hack any more as soon as we switched to
OpenFirmware.

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation

Re: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

[Rick van Rein]

David,

> If you have the NAND hardware connected, then surely your firmware ought
> to be setting the MSRs appropriately?

I broken open a bit more hardware and found an ATA-to-flash interface
between companion chip and flashes.  Sigh, instead of 100 MB/s I am now
limited to 2.4 MB/s and cannot employ this wonderful direct-NAND-stuff.

Thanks for responding though!

-Rick

Re: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS

[David Woodhouse]

On Sat, 2009-12-05 at 17:47 +0000, Rick van Rein wrote:
> David,
> 
> > If you have the NAND hardware connected, then surely your firmware ought
> > to be setting the MSRs appropriately?
> 
> I broken open a bit more hardware and found an ATA-to-flash interface
> between companion chip and flashes.  Sigh, instead of 100 MB/s I am now
> limited to 2.4 MB/s and cannot employ this wonderful direct-NAND-stuff.

The NAND controller on the Geode is only capable of about 3.5MiB/s
anyway. There's a reason we put a new NAND flash controller on OLPC.

-- 
dwmw2