Re: [PATCH] mtd: cfi: Wait for Block Erase operation to finish

Paul Parsons
2012-03-01T17:22:12Z

--- On Thu, 1/3/12, Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
> > OK, I think I've made some progress here.
> >
> > The status transitions around the Erase Resume are as
> follows:
> >
> > [   58.702774] 108: PUTC: 0:
> status=0x00c000c0 // Before CMD(0xd0)
> > [   58.702792] 108: PUTC: 1:
> status=0x00400040 // After CMD(0xd0),CMD(0x70)
> > [   58.702808] 108: PUTC: 2:
> status=0x00000000 // + cfi_udelay(1)
>
> hmm, this is not ideal. The status bits are only valid if
> SR.7 is set if I remember correctly?
> Maybe SR.6 is an exception?
> So reading SR.6 and waiting for it to clear may not work on
> other chips?
> Is there some resume to erase time in the specs?

Yes the spec I have (Intel StrataFlash, 253854-003) says SR[6:1] are valid
only if SR.7=1. It also says (section 13.4) "The Erase Resume command
instructs the corresponding segment to continue erasing, and automatically
clears status register bits SR[7:6]". The flowchart makes no mention of
needing to poll the status register after issuing an Erase Resume command.
The spec makes no mention of Erase Resume time.

It seems to me that waiting for SR[7:6]=00 instead of just SR.6=0 would:
1. Have the same outcome.
2. Be strictly within spec; SR[7:6] have been cleared therefore the Erase
Resume command has been accepted.