From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-yh0-f44.google.com ([209.85.213.44]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VmN3i-0006oh-NX for linux-mtd@lists.infradead.org; Fri, 29 Nov 2013 12:20:35 +0000 Received: by mail-yh0-f44.google.com with SMTP id f64so6727955yha.17 for ; Fri, 29 Nov 2013 04:20:16 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dwmw2@infradead.org Subject: [PATCH v3 21/36] mtd: st_spi_fsm: Update the flash Volatile Configuration Register Date: Fri, 29 Nov 2013 12:19:10 +0000 Message-Id: <1385727565-25794-22-git-send-email-lee.jones@linaro.org> In-Reply-To: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> References: <1385727565-25794-1-git-send-email-lee.jones@linaro.org> Cc: angus.clark@st.com, linus.walleij@linaro.org, Lee Jones , linux-mtd@lists.infradead.org List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for updating a chip's VCR. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 325fd7a..9449005 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -68,6 +68,23 @@ static struct stfsm_seq stfsm_seq_erase_sector = { SEQ_CFG_STARTSEQ), }; +static struct stfsm_seq stfsm_seq_wrvcr = { + .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), + .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WRVCR)), + .seq = { + STFSM_INST_CMD1, + STFSM_INST_CMD2, + STFSM_INST_STA_WR1, + STFSM_INST_STOP, + }, + .seq_cfg = (SEQ_CFG_PADS_1 | + SEQ_CFG_READNOTWRITE | + SEQ_CFG_CSDEASSERT | + SEQ_CFG_STARTSEQ), +}; + static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) { seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | @@ -189,6 +206,21 @@ static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) return 0; } +static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data) +{ + struct stfsm_seq *seq = &stfsm_seq_wrvcr; + + dev_dbg(fsm->dev, "writing VCR 0x%02x\n", data); + + seq->status = (STA_DATA_BYTE1(data) | STA_PADS_1 | STA_CSDEASSERT); + + stfsm_load_seq(fsm, seq); + + stfsm_wait_seq(fsm); + + return 0; +} + /* * SoC reset on 'boot-from-spi' systems * -- 1.8.3.2