From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-we0-f176.google.com ([74.125.82.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WQZB1-0006St-EO for linux-mtd@lists.infradead.org; Thu, 20 Mar 2014 09:22:16 +0000 Received: by mail-we0-f176.google.com with SMTP id x48so363347wes.21 for ; Thu, 20 Mar 2014 02:21:52 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, computersforpeace@gmail.com Subject: [PATCH v6 16/36] mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing mode Date: Thu, 20 Mar 2014 09:20:48 +0000 Message-Id: <1395307268-12721-17-git-send-email-lee.jones@linaro.org> In-Reply-To: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> References: <1395307268-12721-1-git-send-email-lee.jones@linaro.org> Cc: dwmw2@infradead.org, Lee Jones , linux-mtd@lists.infradead.org, Angus.Clark@st.com List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 06e6a52..9d1edf0 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -411,6 +411,28 @@ static struct stfsm_seq stfsm_seq_erase_sector = { SEQ_CFG_STARTSEQ), }; +static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) +{ + seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR)); + seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(FLASH_CMD_WREN) | + SEQ_OPC_CSDEASSERT); + + seq->seq[0] = STFSM_INST_CMD2; + seq->seq[1] = STFSM_INST_CMD1; + seq->seq[2] = STFSM_INST_WAIT; + seq->seq[3] = STFSM_INST_STOP; + + seq->seq_cfg = (SEQ_CFG_PADS_1 | + SEQ_CFG_ERASE | + SEQ_CFG_READNOTWRITE | + SEQ_CFG_CSDEASSERT | + SEQ_CFG_STARTSEQ); + + return 0; +} + static inline int stfsm_is_idle(struct stfsm *fsm) { return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; -- 1.8.3.2