From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lucas Stach To: Brian Norris , David Woodhouse , Thierry Reding , Stephen Warren Subject: [Patch v3 3/5] clk: tegra20: init NDFLASH clock to sensible rate Date: Sun, 10 May 2015 20:30:00 +0200 Message-Id: <1431282602-7137-4-git-send-email-dev@lynxeye.de> In-Reply-To: <1431282602-7137-1-git-send-email-dev@lynxeye.de> References: <1431282602-7137-1-git-send-email-dev@lynxeye.de> Cc: Mark Rutland , Alexandre Courbot , Pawel Moll , Boris BREZILLON , Stefan Agner , devicetree@vger.kernel.org, Rob Herring , linux-mtd@lists.infradead.org, Ezequiel Garcia , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 41272dc..f20424d 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1063,6 +1063,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, + {TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0}, {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ }; -- 2.1.0