[PATCH 09/10] mtd: spi-nor: aspeed: link controller with the ahb clock

Cédric Le Goater
2017-04-06T16:59:22Z

We will need the AHB frequency to set the HCLK settings in the SMC
controller to optimize the reads.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
drivers/mtd/spi-nor/aspeed-smc.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index 3c004dfaf873..1b398303f039 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -10,6 +10,7 @@
*/

#include <linux/bug.h>
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dma-direction.h>
#include <linux/dma-mapping.h>
@@ -119,6 +120,8 @@ struct aspeed_smc_controller {
void __iomem *regs; /* controller registers */
void __iomem *ahb_base; /* per-chip windows resource */

+ struct clk *ahb_clk;
+
/* interrupt handling */
int irq;

@@ -1107,6 +1110,10 @@ static int aspeed_smc_probe(struct platform_device *pdev)
if (IS_ERR(controller->ahb_base))
return PTR_ERR(controller->ahb_base);

+ controller->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(controller->ahb_clk))
+ return PTR_ERR(controller->ahb_clk);
+
aspeed_smc_dma_setup(controller, pdev);

ret = aspeed_smc_setup_flash(controller, np, res);
--
2.7.4