Re: 4 x AMD29LV800B CFI?

[David Woodhouse <dwmw2@infradead.org>]

espin@idiom.com said:
>  Perhaps my h/w setup is insisting that all 4 parts are programmed at
> once?  I see ifdef SOMEONE_ACTUALLY... for width 4 type 32 interleave
> 4; maybe this means generate the right pattern? 

That's around the code for 32-bit flash chips. You don't have 32-bit chips, 
you have 16-bit chips, in 8-bit mode.

I've used the 29LV160, and it's definitely CFI-compliant. Strangely, the 
29LV800 isn't. But the jedec_probe code doesn't yet recognise it. Try 
this...

Index: drivers/mtd/chips/jedec_probe.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/chips/jedec_probe.c,v
retrieving revision 1.6
diff -u -r1.6 jedec_probe.c
--- drivers/mtd/chips/jedec_probe.c	2001/10/22 10:16:08	1.6
+++ drivers/mtd/chips/jedec_probe.c	2001/11/27 11:04:56
@@ -35,6 +35,8 @@
 #define AM29LV800BT	0x22DA
 #define AM29LV160DT	0x22C4
 #define AM29LV160DB	0x2249
+#define AM29LV800BT	0x22DA
+#define AM29LV800BB	0x225B
 
 /* Atmel */
 #define AT49BV16X4	0x00c0
@@ -97,6 +99,30 @@
 #define SIZE_8MiB   23
 
 static const struct amd_flash_info jedec_table[] = {
+	{
+		mfr_id: MANUFACTURER_AMD,
+		dev_id: AM29LV800BT,
+		name: "AMD AM29LV800BT",
+		DevSize: SIZE_1MiB,
+		CmdSet:	P_ID_AMD_STD,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: MANUFACTURER_AMD,
+		dev_id: AM29LV800BB,
+		name: "AMD AM29LV800BB",
+		DevSize: SIZE_1MiB,
+		CmdSet:	P_ID_AMD_STD,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x04000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x10000,15)
+		}
 	{
 		mfr_id: MANUFACTURER_AMD,
 		dev_id: AM29LV160DT,



--
dwmw2