From: Aaron Sierra <asierra@xes-inc.com>
To: linux-mtd@lists.infradead.org,
Brian Norris <computersforpeace@gmail.com>,
David Woodhouse <dwmw2@infradead.org>
Cc: Jordan Friendshuh <jfriendshuh@xes-inc.com>, devicetree@vger.kernel.org
Subject: [PATCH v2] mtd: fsl_upm: Support NAND ECC DTS properties
Date: Sat, 8 Nov 2014 13:11:56 -0600 (CST) [thread overview]
Message-ID: <1854666513.5578.1415473916534.JavaMail.zimbra@xes-inc.com> (raw)
In-Reply-To: <71973089.5152.1415472776826.JavaMail.zimbra@xes-inc.com>
From: Jordan Friendshuh <jfriendshuh@xes-inc.com>
Support the generic nand-ecc-mode and nand-ecc-strength device-tree
properties with the Freescale UPM NAND driver.
This patch preserves the default software ECC mode while adding the
ability to use BCH ECC for larger NAND devices.
Signed-off-by: Jordan Friendshuh <jfriendshuh@xes-inc.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
---
v2:
* Now using ECC mode and strength helpers from of_mtd.h
* ECC mode and strength checking is more robust
.../devicetree/bindings/mtd/fsl-upm-nand.txt | 2 +
drivers/mtd/nand/Kconfig | 1 +
drivers/mtd/nand/fsl_upm.c | 51 +++++++++++++++++++---
3 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
index fce4894..a9906f6 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
@@ -18,6 +18,8 @@ Optional properties:
- chip-delay : chip dependent delay for transferring data from array to
read registers (tR). Required if property "gpios" is not used
(R/B# pins not connected).
+- nand-ecc-mode : as defined by nand.txt ("soft" and "soft_bch", only).
+- nand-ecc-strength : as defined by nand.txt.
Each flash chip described may optionally contain additional sub-nodes
describing partitions of the address space. See partition.txt for more
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index f1cf503..85c0243 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -439,6 +439,7 @@ config MTD_NAND_FSL_UPM
tristate "Support for NAND on Freescale UPM"
depends on PPC_83xx || PPC_85xx
select FSL_LBC
+ select MTD_NAND_ECC_BCH
help
Enables support for NAND Flash chips wired onto Freescale PowerPC
processor localbus with User-Programmable Machine support.
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 4d203e8..8f38447 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -18,6 +18,7 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
+#include <linux/of_mtd.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
@@ -160,6 +161,11 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
int ret;
struct device_node *flash_np;
struct mtd_part_parser_data ppdata;
+ int mode, strength;
+
+ flash_np = of_get_next_child(upm_np, NULL);
+ if (!flash_np)
+ return -ENODEV;
fun->chip.IO_ADDR_R = fun->io_base;
fun->chip.IO_ADDR_W = fun->io_base;
@@ -168,7 +174,46 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
fun->chip.read_byte = fun_read_byte;
fun->chip.read_buf = fun_read_buf;
fun->chip.write_buf = fun_write_buf;
- fun->chip.ecc.mode = NAND_ECC_SOFT;
+
+ /*
+ * If nand-ecc-strength < 0, require ECC_SOFT, error otherwise.
+ * If nand-ecc-strength == 0, error.
+ * If nand-ecc-strength == 1, require ECC_SOFT, error otherwise.
+ * If nand-ecc-strength > 1, force ECC_SOFT_BCH (warn on mode mismatch).
+ */
+ mode = of_get_nand_ecc_mode(flash_np);
+ strength = of_get_nand_ecc_strength(flash_np);
+ if (!of_property_read_bool(flash_np, "nand-ecc-mode")) {
+ dev_info(fun->dev, "ECC mode defaulting to 'soft'");
+ mode = NAND_ECC_SOFT;
+ } else if (mode != NAND_ECC_SOFT && mode != NAND_ECC_SOFT_BCH) {
+ dev_err(fun->dev, "ECC mode in device tree is unsupported");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* We know mode is either NAND_ECC_SOFT or NAND_ECC_SOFT_BCH */
+ if (strength < 0 && mode == NAND_ECC_SOFT_BCH) {
+ dev_err(fun->dev,
+ "ECC BCH mode requires nand-ecc-strength property");
+ ret = -EINVAL;
+ goto err;
+ } else if (strength == 0) {
+ dev_err(fun->dev, "ECC strength of 0 bits is unsupported");
+ ret = -EINVAL;
+ goto err;
+ } else if (strength == 1 && mode == NAND_ECC_SOFT_BCH) {
+ dev_err(fun->dev, "ECC BCH mode requires > 1-bit strength");
+ ret = -EINVAL;
+ goto err;
+ } else if (strength > 1 && mode == NAND_ECC_SOFT) {
+ dev_warn(fun->dev,
+ "Forcing ECC BCH due to %d-bit strength\n", strength);
+ mode = NAND_ECC_SOFT_BCH;
+ }
+ fun->chip.ecc.mode = mode;
+ fun->chip.ecc.strength = strength;
+
if (fun->mchip_count > 1)
fun->chip.select_chip = fun_select_chip;
@@ -178,10 +223,6 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
fun->mtd.priv = &fun->chip;
fun->mtd.owner = THIS_MODULE;
- flash_np = of_get_next_child(upm_np, NULL);
- if (!flash_np)
- return -ENODEV;
-
fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
flash_np->name);
if (!fun->mtd.name) {
--
1.9.1
next parent reply other threads:[~2014-11-08 19:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <71973089.5152.1415472776826.JavaMail.zimbra@xes-inc.com>
2014-11-08 19:11 ` Aaron Sierra [this message]
2014-11-23 0:55 ` [PATCH v2] mtd: fsl_upm: Support NAND ECC DTS properties Ezequiel Garcia
2014-11-24 15:22 ` Aaron Sierra
2014-11-25 20:08 ` Ezequiel Garcia
2014-11-25 22:19 ` Aaron Sierra
2014-11-25 22:42 ` Ezequiel Garcia
2014-11-25 23:23 ` Aaron Sierra
2014-12-17 0:35 ` Brian Norris
2014-12-17 2:11 ` Aaron Sierra
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