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From: Michael Walle <michael@walle.cc>
To: Fabio Estevam <festevam@gmail.com>
Cc: tudor.ambarus@linaro.org, pratyush@kernel.org,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	linux-mtd@lists.infradead.org, Fabio Estevam <festevam@denx.de>,
	tkuw584924@gmail.com
Subject: Re: [PATCH] mtd: spi-nor: micron-st: Add support for mt25qu01g
Date: Tue, 24 Oct 2023 15:59:41 +0200	[thread overview]
Message-ID: <1ac379836d4e1e3f7bec565ba7c9bc49@walle.cc> (raw)
In-Reply-To: <CAOMZO5BNcFZcLsi+0Qx5zxwTHqzrnUsGgb0AMptAtY4Kj9Apmg@mail.gmail.com>

Hi,

>> > +             .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
>> > +             .name = "mt25qu01g",
>> > +             .size = SZ_128M,
>> 
>> Not needed, parsed by SFDP.
>> 
>> > +             .flags = NO_CHIP_ERASE,
>> 
>> Is it fair to assume that this is the usual case for multi die chips?
>> See also,
>> https://lore.kernel.org/linux-mtd/cover.1680849425.git.Takahiro.Kuwano@infineon.com/
>> 
>> So "if n_dice > 1" will implicitly be NO_CHIP_ERASE. n_dice should be
>> parsed from SFDP.
>> 
>> > +             .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
>> 
>> .no_sfdp_flags are legacy and shouldn't be used with new flashes.
> 
> I tried your suggestion and tested with the change below:

You'd need to change the core to assume there is no chip
erase support if "n_dice > 1". So first step would be that
your SPI flash will successfully parse the SFDP and set n_dice
correctly. Then adapt the core to set SNOR_F_NO_OP_CHIP_ERASE
if "n_dice > 1".
The goal here is to avoid any entry in our database at all and
support this flash out of the box by just parsing SFDP correctly.

Which leaves us with this damn USE_FSR..

> ~# cat 
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id
> 20bb21104400
> ~# cat 
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer
> st
> ~# cat 
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/partname
> mt25qu01g
> ~# xxd -p  
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
> 53464450060101ff00060110300000ff84000102800000ffffffffffffff
> ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b
> 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e
> 03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff
> ffffffffffffffffffe7ffff21dcffff
> ~# md5sum  
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
> 9d28d1b11de8b15ba9152644219d9a78
> /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp

thanks!

-michael

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  reply	other threads:[~2023-10-24 13:59 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23 21:38 [PATCH] mtd: spi-nor: micron-st: Add support for mt25qu01g Fabio Estevam
2023-10-24  6:01 ` Tudor Ambarus
2023-10-24 13:57   ` Fabio Estevam
2023-10-24 14:23     ` Tudor Ambarus
2023-10-24  9:26 ` Michael Walle
2023-10-24 11:43   ` Fabio Estevam
2023-10-24 13:59     ` Michael Walle [this message]
2023-10-24 15:47       ` Fabio Estevam
2023-10-24 15:53         ` Tudor Ambarus
2023-10-24 16:20           ` Fabio Estevam
2023-10-24 16:36             ` Michael Walle
2023-10-24 16:43               ` Fabio Estevam
2023-10-25  3:34                 ` Tudor Ambarus
2023-10-25 11:56                   ` Fabio Estevam
2023-10-25 17:35                     ` Fabio Estevam
2023-10-26  6:33                       ` Michael Walle
2023-10-26 11:25                         ` Fabio Estevam

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