MTD on intel 28F320B3 flash memory

MTD on intel 28F320B3 flash memory

[Peter De Schrijver]

Hi,

Is this type of flash memory supported ? It seems to use the standard 
intel/sharp command set (command set #3), although it's not fully CFI 
compliant.

Thanks,

Peter.



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Re: MTD on intel 28F320B3 flash memory

[David Woodhouse]

Your From address is broken.

On Fri, 17 Nov 2000, Peter De Schrijver wrote:

> Is this type of flash memory supported ? It seems to use the standard
> intel/sharp command set (command set #3), although it's not fully CFI
> compliant.

We only explicitly support the Intel 'Extended' command set. But IIRC the
'Standard' command set is almost identical, apart from some operations
which we don't support yet anyway.

Try making it use the cfi_cmdset_0001 code and see what happens.

-- 
dwmw2




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Re: MTD on intel 28F320B3 flash memory

[Nick Ivanter]

Are you sure it's not CFI complaint?
I've been working with 28F640 which is CFI complaint and
is detected and operated by the existing code fairly well.
I believe the only difference between 28F640 and 28F320 is
that the latter is smaller. They are even described in a
single datasheet.

Nick

Peter De Schrijver wrote:

> Hi,
>
> Is this type of flash memory supported ? It seems to use the standard
> intel/sharp command set (command set #3), although it's not fully CFI
> compliant.
>
> Thanks,
>
> Peter.
>
> To unsubscribe, send "unsubscribe mtd" to majordomo@infradead.org



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Re: MTD on intel 28F320B3 flash memory

[Mike Hill]

The CFI code will not work with this chip without modification.

The 28F320B3 is a BOOT BLOCK flash part.  It contains Eight 8K regions and
63 64K regions.  The CFI code assumes that all regions are of the same size.
I am currently using this part in a design.  To get around this problem, I
changed the CFI code to treat the 8K regions as a single 64K region.

-Mike

----- Original Message -----
From: "Nick Ivanter" <nick@auriga.ru>
To: "Peter De Schrijver" <p2@portablue.linux-apollo.org>
Cc: <mtd@infradead.org>
Sent: Friday, November 17, 2000 3:44 AM
Subject: Re: MTD on intel 28F320B3 flash memory


> Are you sure it's not CFI complaint?
> I've been working with 28F640 which is CFI complaint and
> is detected and operated by the existing code fairly well.
> I believe the only difference between 28F640 and 28F320 is
> that the latter is smaller. They are even described in a
> single datasheet.
>
> Nick
>
> Peter De Schrijver wrote:
>
> > Hi,
> >
> > Is this type of flash memory supported ? It seems to use the standard
> > intel/sharp command set (command set #3), although it's not fully CFI
> > compliant.
> >
> > Thanks,
> >
> > Peter.
> >
> > To unsubscribe, send "unsubscribe mtd" to majordomo@infradead.org
>
>
>
> To unsubscribe, send "unsubscribe mtd" to majordomo@infradead.org



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Re: MTD on intel 28F320B3 flash memory

[David Woodhouse]

mhill@bustech.com said:
>  The 28F320B3 is a BOOT BLOCK flash part.  It contains Eight 8K
> regions and 63 64K regions.  The CFI code assumes that all regions are
> of the same size. I am currently using this part in a design.  To get
> around this problem, I changed the CFI code to treat the 8K regions as
> a single 64K region. 

I think that's the correct way do do things. I don't think the MTD layer 
needs to handle variable erase sizes within a single MTD partition. Either 
your CFI driver registers a single device with 64K erasesize, or it 
registers two devices, one with 8K erasesize and the remainder with 64K 
erasesize.

I can't think of any situation in which you'd want to _use_ the multiple 
erasesize without actually using the boot blocks for a separate purpose to 
the remainder of the flash, in which case they should be in different MTD 
devices anyway, as far as the MTD layer is concerned.

--
dwmw2




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Re: MTD on intel 28F320B3 flash memory

[Nicolas Pitre]

On Fri, 17 Nov 2000, David Woodhouse wrote:

>
> mhill@bustech.com said:
> >  The 28F320B3 is a BOOT BLOCK flash part.  It contains Eight 8K
> > regions and 63 64K regions.  The CFI code assumes that all regions are
> > of the same size. I am currently using this part in a design.  To get
> > around this problem, I changed the CFI code to treat the 8K regions as
> > a single 64K region.
>
> I think that's the correct way do do things. I don't think the MTD layer
> needs to handle variable erase sizes within a single MTD partition. Either
> your CFI driver registers a single device with 64K erasesize, or it
> registers two devices, one with 8K erasesize and the remainder with 64K
> erasesize.

But then you have problem with concurent access to the chip... unless the
code is tweaked so both mtd devices share the same spinlock and wq.


Nicolas



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Re: MTD on intel 28F320B3 flash memory

[David Woodhouse]

nico@cam.org said:
>  But then you have problem with concurent access to the chip... unless
> the code is tweaked so both mtd devices share the same spinlock and
> wq. 

Yep. That's not difficult. Actually, I think that's why the struct flchip 
contains both a spin_lock_t *mutex and the spinlock itself - so that you 
can point to a spinlock elsewhere if you want to.

--
dwmw2




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Re: MTD on intel 28F320B3 flash memory

[David Woodhouse]

nico@cam.org said:
>  But then you have problem with concurent access to the chip... unless
> the code is tweaked so both mtd devices share the same spinlock and
> wq.

Upon further consideration...

They can just be different 'partitions' of the same underlying device - they
only appear as two separate devices to the upper layers - just like normal 
MTD partitioning.

All we have to do is make the erase routine aware of the nature of the 
chip, and make sure it correctly erases the correct amount of data, 
according to the length passed in as part of the erase request. We have to 
do that anyway, even in the case where we want to pretend it's all 64KiB.

Then it doesn't matter if the registered MTD partitions actually have 
different erase sizes. 

--
dwmw2




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