Problems with cfi_cmdset_0001

Shane Nay
2000-12-02T11:57:47Z

Okay, I've been reading the PDF for Strataflash, by Intel. And I've traced
my problems with the write routines in MTD down to two problems, the Block
address, and the word write problem. The command address isn't properly
interpretted for this chip. I'm not sure what the CFI spec is, but I
think:
cmd_adr=adr & ~(wbufsize-1);
is wrong. (Well, maybe it's different chip to chip, but I know it's wrong
for this chip)

It should compute the top of the block via the erasesize and size.
cmd_adr=mtd->erasesize*((int)(adr/mtd->erasesize));

Now, this fixes the Block address. The other problem though is
significantly nastier.

Okay, MTD seems to think that it can write twice as much data as it can to
a device at a time in write_buffer mode, which is all together wrong. My
configuration is two x8 chips interleaved on a 16 bit bus. Basically...,
its thinking we have two x16 chips on a 32 bit bus before streaming, but
then streams the data the right way, but twice as much as it said it would.
(It says, I'm sending 16 words, then sends 32 of them instead, which as
you could imagine, is quite confusing to the poor flash chips)

In any event. I've got the block address problem fixed up in the code with
the afore mentioned code. The other problem I'm still working on.
However, my code is so removed at this point from MTD base since I had too
many other things at play with MTD code to properly trace my problem, and
now I have a cleaner version of the code for XIP. So I'm not sure I'm
going to roll all my changes into cfi_cmdset_0001. Who is the maintainer
of this file BTW? I'll try to make patches for him/her to fix these
problems.

Thanks,
Shane.

(Or maybe my extremely tired brain is mis-interpretting..., if I'm wrong,
tell me so :)