From: swahl@brecis.com (Steve Wahl)
To: linux-mtd@lists.infradead.org
Subject: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)
Date: Mon, 17 Mar 2003 10:19:28 -0600 [thread overview]
Message-ID: <20030317101928.J1745@brecis.com> (raw)
In-Reply-To: <1047916461.11517.85.camel@tubarao>; from tharbaugh@lnxi.com on Mon, Mar 17, 2003 at 08:54:21AM -0700
On Mon, Mar 17, 2003 at 08:54:21AM -0700, Thayne Harbaugh wrote:
> On Wed, 2003-03-12 at 14:43, Steve Wahl wrote:
> > On Wed, Mar 12, 2003 at 12:12:12PM -0500, John Burch wrote:
>
> <snip>
>
> > > The status register (including DQ5) won't reflect actual data until
> > > a reset command is issued,
> >
> > This I think is a misunderstanding or misstatement on your part. The
> > reads WILL return to actual data without a reset upon successful
> > completion of the operation. Only on a failure does software need to
> > issue the reset to return to reading data!
>
> Big question: how is it know if status bits are being read or the real
> data that was written to an address? I have read many data sheets and I
> don't recall any of them discussing this concern.
Easy, at least in theory. If two consecutive reads are the same, then
the DQ6 isn't toggling any longer, therfore you are reading data.
Only if the two consecutive reads are different can you assume that
you read the status register -- and you can only assume the FIRST read
was a status register, because the second read could have been after
changing to data mode.
But, outside of easy theories, there's a couple of gotchas in there.
I've read at least one data sheet that suggested that the switch from
the status register to the data "register" happens asyncronously to
processor reads, so it is possible, though very unlikely, to get some
bits from the status register and some bits from the actual data
within a single read -- if the read happens at the exact instance that
the chip is switching from one mode to the other.
I have never seen any code that takes this into account -- sample
code, data sheet flow charts, etc. I think this may, however, have
something to do with what you wrote: "I do know, however, that several
manufactures recommend that the final status should be checked an
additional two times before a success is reported." I'd be interested
to see specific data sheets or application notes that do this.
--> Steve
next prev parent reply other threads:[~2003-03-17 16:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-12 0:25 DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning) Thayne Harbaugh
2003-03-12 15:44 ` John Burch
2003-03-12 16:35 ` Thayne Harbaugh
2003-03-12 16:27 ` Steve Wahl
2003-03-12 17:12 ` John Burch
2003-03-12 21:43 ` Steve Wahl
2003-03-12 22:17 ` John Burch
2003-03-13 7:17 ` David Woodhouse
2003-03-13 7:26 ` Russ Dill
2003-03-17 15:54 ` Thayne Harbaugh
2003-03-17 16:09 ` John Burch
2003-03-17 16:19 ` Steve Wahl [this message]
2003-03-17 18:27 ` Thayne Harbaugh
2003-03-18 16:51 ` Steve Wahl
2003-03-18 17:22 ` Thayne Harbaugh
2003-03-17 15:40 ` Thayne Harbaugh
2003-03-17 18:38 ` Thayne Harbaugh
2003-03-19 0:23 ` Thayne Harbaugh
2003-03-19 15:56 ` Steve Wahl
2003-03-19 19:38 ` Thayne Harbaugh
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