Re: Handling multiple NAND chips -- take 2

[Thomas Gleixner <tglx@linutronix.de>]

On Wednesday 25 February 2004 18:44, J.D. Bakker wrote:

> * Assumption: all devices are the same type and size.
> * No support (yet) for building a wider data bus through putting
> multiple devices in parallel
> * All detected devices are concatenated and represented as one large
> linear array of pages
> * All devices are soldered to a motherboard. We are not interested in
> taking devices out of the array.
> * No optimizations (yet) wrt accessing device n while device m is
> busy. Easier to get working code fast than to get fast code working,
> and I don't see a way to take advantage of parallelism without
> modifying higher layers
If all devices share the same control lines (except CS) then an optimization 
of accessing device n while m is busy can be rather complex. 

I have already done some tests with 4 chips on a board. The scenario is, that 
all bus /  control lines except the CS lines are shared over all devices.

The idea is to add 3 pointers to the nand structure. 
p_state		points to state 
p_chip_lock	points to chip_lock
p_wq			points to wq

The pointers can either be initialized in the chip driver or are initialized 
by the nand_scan function to the default fields (state, chip_lock, wq). This 
would not break any existing chipdrivers.

All accesses to state, chiplock and wq must be modified so the access happens 
through the pointers instead of accessing the fields directly.

For your case you must initialize the pointers of chip 2 - 8 to share the 
state, chip_lock and wq field of the first chip. The hwcontrol function is 
shared for all chips.

Then you can use the existing mtdconcat layer to build partition(s) over 
several chips. 

This solution supports 
* different chip type / sizes
* removable devices 
* flexible partitioning

-- 
Thomas
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