Re: FW: DOC Mil Plus 32 question erase size erase shift????

["Thomas Gleixner" <tglx@linutronix.de>]

On Tuesday 22 June 2004 14:49, Carlos, John J USAATC wrote:
> What should the buffer size be for an erase block in memory.  How is that
> value tied to the chip geometry???

Would you please be so kind and answer the questions, if we should be able to 
help you.

1. Is the device running in x16 mode?
If yes, then we have to fix this first, as it is not supported by nand_base.c 
at the moment. nand_scan() has to be made aware of this.

2. What's the output of the chip detection routine including nand_scan() ?

3. What did you change in nand_bbt.c ? 

4. What's the bbt structure you pass to nand_scan_bbt ?

5. Can you send me your driver code including he modifications to nand_base.c 
and nand_bbt.c, so I can have a look ?

-- 
Thomas
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