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* FW: DOC Mil Plus 32 question erase size erase shift????
@ 2004-06-22 12:49 Carlos, John J USAATC
  2004-06-22 13:01 ` Thomas Gleixner
  0 siblings, 1 reply; 2+ messages in thread
From: Carlos, John J USAATC @ 2004-06-22 12:49 UTC (permalink / raw)
  To: linux-mtd

What should the buffer size be for an erase block in memory.  How is that
value tied to the chip geometry???

Thanks,
John

-----Original Message-----
From: Thomas Gleixner [mailto:tglx@linutronix.de] 
Sent: Monday, June 21, 2004 5:28 PM
To: Carlos, John J USAATC
Subject: Re: DOC Mil Plus 32 question erase size erase shift????


On Monday 21 June 2004 23:32, you wrote:
> Hi Thomas,
>
>   I will look again at where I get the value of erasesize.  I thought 
> I read it in the DOC pdf file???  I am not at work now so in the 
> morning I will see where I have gone wrong and let you know.

Oh, the device operates in interleave-2 16 bit mode. This is a seperate
issue 
which we have to check.

-- 
Thomas _____________________________________________________________________
>From slash dot org
"When customers are visiting, engineers are not allowed to wear ties. 
That way the customer can tell who is the engineer and who is the 
salesman (and therefore whom to believe.). Ties cut off blood flow 
to the brain, making it easier for the salesmen to do their jobs." 
_____________________________________________________________________
linutronix - competence in embedded & realtime linux
http://www.linutronix.de
mail: tglx@linutronix.de

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: FW: DOC Mil Plus 32 question erase size erase shift????
  2004-06-22 12:49 FW: DOC Mil Plus 32 question erase size erase shift???? Carlos, John J USAATC
@ 2004-06-22 13:01 ` Thomas Gleixner
  0 siblings, 0 replies; 2+ messages in thread
From: Thomas Gleixner @ 2004-06-22 13:01 UTC (permalink / raw)
  To: linux-mtd

On Tuesday 22 June 2004 14:49, Carlos, John J USAATC wrote:
> What should the buffer size be for an erase block in memory.  How is that
> value tied to the chip geometry???

Would you please be so kind and answer the questions, if we should be able to 
help you.

1. Is the device running in x16 mode?
If yes, then we have to fix this first, as it is not supported by nand_base.c 
at the moment. nand_scan() has to be made aware of this.

2. What's the output of the chip detection routine including nand_scan() ?

3. What did you change in nand_bbt.c ? 

4. What's the bbt structure you pass to nand_scan_bbt ?

5. Can you send me your driver code including he modifications to nand_base.c 
and nand_bbt.c, so I can have a look ?

-- 
Thomas
_____________________________________________________________________
From slash dot org
"When customers are visiting, engineers are not allowed to wear ties. 
That way the customer can tell who is the engineer and who is the 
salesman (and therefore whom to believe.). Ties cut off blood flow 
to the brain, making it easier for the salesmen to do their jobs." 
_____________________________________________________________________
linutronix - competence in embedded & realtime linux
http://www.linutronix.de
mail: tglx@linutronix.de

^ permalink raw reply	[flat|nested] 2+ messages in thread

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