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From: "Thomas Gleixner" <tglx@linutronix.de>
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Date: Tue, 22 Jun 2004 15:01:29 +0200
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Subject: Re: FW: DOC Mil Plus 32 question erase size erase shift????
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On Tuesday 22 June 2004 14:49, Carlos, John J USAATC wrote:
> What should the buffer size be for an erase block in memory.  How is that
> value tied to the chip geometry???

Would you please be so kind and answer the questions, if we should be able =
to=20
help you.

1. Is the device running in x16 mode?
If yes, then we have to fix this first, as it is not supported by nand_base=
=2Ec=20
at the moment. nand_scan() has to be made aware of this.

2. What's the output of the chip detection routine including nand_scan() ?

3. What did you change in nand_bbt.c ?=20

4. What's the bbt structure you pass to nand_scan_bbt ?

5. Can you send me your driver code including he modifications to nand_base=
=2Ec=20
and nand_bbt.c, so I can have a look ?

=2D-=20
Thomas
_____________________________________________________________________
=46rom slash dot org
"When customers are visiting, engineers are not allowed to wear ties.=20
That way the customer can tell who is the engineer and who is the=20
salesman (and therefore whom to believe.). Ties cut off blood flow=20
to the brain, making it easier for the salesmen to do their jobs."=20
_____________________________________________________________________
linutronix - competence in embedded & realtime linux
http://www.linutronix.de
mail: tglx@linutronix.de