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From: Charles Manning <manningc2@actrix.gen.nz>
To: linux-mtd@lists.infradead.org
Cc: "Wolfgang Mües" <wolfgang.mues@auerswald.de>
Subject: Re: Questions about NAND (double)bit errors
Date: Thu, 16 Feb 2006 16:17:04 +1300	[thread overview]
Message-ID: <200602161617.04905.manningc2@actrix.gen.nz> (raw)
In-Reply-To: <200602141510.12749.wolfgang.mues@auerswald.de>

On Wednesday 15 February 2006 03:10, Wolfgang Mües wrote:
> Hello Charles,
>
> Charles Manning wrote:
> > * YAFFS is very conservative on dealing with ECC failures. YAFFS retires
> > a block if one ECC failure is seen. JFFS2, IIRC allows five of so failure
> > before retiring a block. The Toshiba folk have told me that if a block is
> > going bad, it is most likely to start displaying recoverable 1-bit errors
> > before displaying non-recoverable multi-bit errors. Thus, YAFFS will
> > potentially perform differently in this area.
>
> About bad block detection: what is your oppinion about partitioning the
> flash (the programs in a read-only partition, the data in r/w).

This gets fs specific. With YAFFS (and I assume JFFS2, but consult an expert), 
grabage collection will force read-only files to get rewritten occasionally. 
Thus for ultimate reliability it is probably a GoodIdea to seperate the 
read-only stuff into a seperate partition. This is also a GoodIdea in that a 
smaller partition mounts faster (true for YAFFS and JFFS2). So if all your 
kernel + mount stuff is seperated from your rw stuff things will probably dgo 
better.
>
> How about detection of ECC errors in read only partitions?

ECC should be done on both rw and read-only partitions. Sometimes NAND gets 
read disturbs which would impact on read-only partitions. Also, write 
disturbs from writes to one partition can still corrupt a read-only partition 
on the same chip.

>
> > One important factor, IMHO, is how you handle the write protect pin on
> > the NAND. Some people tie the WP to the power supply failure flag. IMHO
> > this is a bad thing to do since it can cause incomplete writes to happen
> > if the wp is asserted during a write or erase cycle.
>
> I have checked this.
>
> WP is tied to VCC, and VCC is stable at least 500ms after a power fail
> detect.

500ms is long enough to grow a beard.

There's been some interesting discussion over in yaffs-land on this. If you 
don't subscribe to yaffs list then you can catch up on the yaffs archive.

-- Charles

  reply	other threads:[~2006-02-16  3:14 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-02-02 11:12 Questions about NAND (double)bit errors Wolfgang Mües
2006-02-08 22:26 ` Charles Manning
2006-02-10  8:28   ` Wolfgang Mües
2006-02-14 14:10   ` Wolfgang Mües
2006-02-16  3:17     ` Charles Manning [this message]
2006-02-16  8:30       ` Wolfgang Mües
2006-02-16 22:08       ` Jamie Lokier

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