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From: Charles Manning <manningc2@actrix.gen.nz>
To: "Russ Dill" <russ.dill@gmail.com>
Date: Sun, 19 Feb 2006 13:29:00 +1300
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Cc: linux-mtd@lists.infradead.org, yaffs@stoneboat.aleph1.co.uk
Subject: Re: [Yaffs] bit error rates --> a vendor speaks
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On Sunday 19 February 2006 07:11, Russ Dill wrote:
> > Some words about Reed Solomon.
> >
> > Reed Solomon needs hardware support for performance reasons. Efficient
> > usage of Reed Solomon requires a different Data / RS-code layout:
>
> At what level is hardware support required? I'm involved in the design
> of a new system with a 466Mhz 80200. Should fpga considerations be
> mode for ecc correction? What sort of logic would be best to put in
> the fpga?

If you have NAND going past or through the FPGA then thinking about RS or ECC 
is a GoodIdea.

ECC is pretty expensive (yaffs_ecc.c is a bit faster than nand_ecc.c, but 
still requires quite a bit of computation). From what I've heard, RS is a lot 
more expensive.

I have not yet looked at RS yet, but I "pencil designed" a fast and simple ECC 
scheme that needs approx 22 flipflops + some other gates a while ago. This 
mechanism is used pretty much as follows:

1) Clear flipflops.
2) Transfer data
3) Read calculated ECC out of flipflops.

So the actual correction is still done in software, but the expensive part - 
the calculation - is done in hw. This gets you most of the way there with 
limited hw costs.

I hunch that you could do something similar for RS.

-- CHarles