Re: FPGA NAND Interface tips

[Ben Dooks <ben-mtd@fluff.org>]

On Thu, Feb 23, 2006 at 10:07:36PM -0700, Russ Dill wrote:
> I'm providing some input on the NAND wire up, and FPGA design on a new
> board (80200 + FPGA).  I'm currently using rtc_from4.c and s3c2410.c
> as examples.
> 
> So I'm thinking the following for a basic setup:
> 
> reed solomon encoder
> Bit in the FPGA to reset the reed solomon encoder
> place in the FPGA to read out rs codes from last written/read block
> CLE/ALE as address lines
> Read/Busy connected as gpio/interrupt (multiple chips connect to multiple lines)

these sound like good ideas.
 
> Also, when writing/reading to a single address, the 80200 will not
> burst, and round trip time is horrid, especially when talking to IO
> devices. Would a FIFO with a 32 byte interface be a good solution to
> this? maybe with 16 entries (512 bytes)? I realize that DMA would be
> more ideal, but a fifo seems like it might be simplier.

you might also think about a way of writing cmd+addr in one go, or
at-least the address cycles.
 
> Does anyone have any paticular pet peeves when dealing with their NAND
> interface?
> 
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Ben (ben@fluff.org, http://www.fluff.org/)

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