Re: [MTD/NAND] Blackfin NFC driver DMA bug ?

Bryan Wu
2008-02-22T02:52:52Z

On Fri, Feb 22, 2008 at 1:58 AM, Ivan Djelic <ivan.djelic@parrot.com> wrote:
> Hello All,
>
> While working on a NAND flash MTD driver, I came across the following piece of
> code in the Blackfin bf5xx NAND flash controller driver:
>

Thanks, I am always here to answer questions, -;)

> >From linux-2.6.24.2, file bf5xx_nand.c:418, function bf5xx_nand_dma_rw():
>
> /*
> * Before starting a dma transfer, be sure to invalidate/flush
> * the cache over the address range of your DMA buffer to
> * prevent cache coherency problems. Otherwise very subtle bugs
> * can be introduced to your driver.
> */
> if (is_read)
> invalidate_dcache_range((unsigned int)buf,
> (unsigned int)(buf + page_size));
> else
> flush_dcache_range((unsigned int)buf,
> (unsigned int)(buf + page_size));
>
> Since 'buf' is allocated outside MTD, are we allowed to assume it is
> cache-aligned ? Because if it's not, invalidating dcache on read is not enough
> to prevent cache coherency problems. For instance, a cache line partially
> spanning across the buffer address range could be flushed just after DMA has
> completed, corrupting DMA data in the process...

Oh, I am not fully understand your concern. The code is invalidating
or flushing buf before DMA operation.
And invalidate and flush operation is OK for buf which is not
cache-aligned on Blackfin arch. it also should be
OK for other arch.

-Bryan