Re: [MTD/NAND] Blackfin NFC driver DMA bug ?

Bryan Wu
2008-02-25T10:29:43Z

On Fri, Feb 22, 2008 at 3:05 PM, David Woodhouse <dwmw2@infradead.org> wrote:
>
> On Fri, 2008-02-22 at 10:52 +0800, Bryan Wu wrote:
> > Oh, I am not fully understand your concern. The code is invalidating
> > or flushing buf before DMA operation.
> > And invalidate and flush operation is OK for buf which is not
> > cache-aligned on Blackfin arch. it also should be
> > OK for other arch.
>
> The problem occurs when your buffer is not aligned at the beginning of a
> cache line. If there is other data on the _same_ cache line as your
> buffer, and you invalidate the cache, then you may cause data loss
> outside the buffer.
>

Yes, I understand that. I prefer to make sure this buffer issue in the
MTD core API.

> Also, in some systems you must make sure that allocations to be used for
> DMA are from a certain memory pool.
>
> As for the original question... I'm not sure. At the moment I don't
> believe it's true that all such buffers are suitable for DMA. Perhaps it
> would be sensible for us to redefine the MTD API so that it is required
> (and fix the users).
>

Exactly, maybe xxx_nand_dma_read() and xxx_nand_dma_write().
The buffer for this DMA functions should be cache-aligned.

> For a long time, flash I/O was always done by the CPU instead of DMA, so
> it wasn't an interesting question. I did start wondering when I
> implemented support for the CAFÉ controller on OLPC, but then that
> turned out to need bounce buffers anyway so it escaped my attention
> again.
>

We might need to add DMA support in the MTD NAND interface, because
more and more SoC support on-chip NAND controller with DMA support.

Thanks a lot
-Bryan Wu