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Date: Tue, 17 Mar 2009 22:27:35 +0300
From: Anton Vorontsov <avorontsov@ru.mvista.com>
To: Wolfgang Grandegegr <wg@grandegger.com>
Subject: Re: [PATCH 1/4] NAND: FSL-UPM: add multi chip support
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On Tue, Mar 17, 2009 at 10:12:19AM +0100, Wolfgang Grandegegr wrote:
> From: Wolfgang Grandegger <wg@grandegger.com>
> 
> This patch adds support for multi-chip NAND devices to the FSL-UPM
> driver. This requires support for multiple GPIOs for the RNB pins.
> 
> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
> ---
>  drivers/mtd/nand/fsl_upm.c |   90 +++++++++++++++++++++++++++++++++----------
>  1 files changed, 69 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
> index 7815a40..ca7e85a 100644
> --- a/drivers/mtd/nand/fsl_upm.c
> +++ b/drivers/mtd/nand/fsl_upm.c
> @@ -23,6 +23,8 @@
>  #include <linux/io.h>
>  #include <asm/fsl_lbc.h>
>  
> +#define FSL_UPM_NAND_MAX_CHIPS 4

Is there any reason to hardcode max chips? Some obscure limit in the
UPMs maybe?

Otherwise we'd better allocate the rnb_gpios dynamically, depending
on the num-chips property.

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2