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From: David Brownell <david-b@pacbell.net>
To: "vimal singh" <vimalsingh@ti.com>
Subject: Re: [PATCH 2/2] NAND on DM355: Add 4-bit ECC support for large page
	NAND chips
Date: Thu, 7 May 2009 02:11:05 -0700
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On Thursday 07 May 2009, vimal singh wrote:
> > Comments would be good, highlighting (a) byte 5 is reserved,
> > it's the manufacturer bad block marker, (b) 8 bytes @16 are
> > expected by JFFS2.  Not everyone will "just know" those.
>
> How about leaving bytes '4' and '5' for bad block marker, to support 16-bit
> NAND parts too.

This 4-bit ECC engine only works for 8-bit wide parts ...
or are you suggesting that in case TI re-engineers that
engine in the future?