Re: [PATCH 2.6.30-rc6 3/3] NAND: Add 4-bit ECC support for large page NAND chips

Troy Kisky
2009-05-21T00:23:39Z

>
> I explored nand_bbt, jffs2 using the OOB area.
>
> This is what I found -
> 2 bytes at offset 0: BB markers
> 4 bytes at offset 8: BBT magic number/data
> 1 byte at offset 12: BBT version
> 8 bytes at offset 16: JFFS2 clear markers
>
> So, it is better to start with offset 24 (there are few bytes in between, but it is better to leave them as-is).
>
> Dave,
>
> Did you have any comments?
>
> Thanks
> Sneha

If you have to move the ECC anyway, there really isn't a further compatibility
problem with moving the JFFS2 bytes as well.

0-1 : BB marker
2-23 : Free space (JFFS2 will use)
24-63 : 4 x 10 bytes of ecc.

This way, if the default ecc layout patch that I submitted is ever accepted, the code in this
patch can be removed.

Troy