RE: [patch 3/3] mtd-nand: DaVinci: Add 4-bit ECC support for large page NAND chips

Paulraj, Sandeep
2009-08-28T10:22:01Z

Dave,

I've already sent the patch to U-Boot and it has been accepted. Its in the nand next branch. For things to become fully functional i'll need a syncs between the various branches of U-Boot. I'll have to enable stuff in the DM355 and Dm365 configs

since you ask about the U-Boot NAND driver, its based on old TI releases. And i'll tell you the reason why i decided that. The current DaVinci NAND driver in the kernel seems to have issues. 4 BIT ECC correction does not take place in DM365. But random delays in the from of printks seem to help. We are debugging and once that is done i can send an updated U-Boot NAND driver based on your NAND kernel driver

Thanks,
Sandeep
________________________________________
From: David Brownell [david-b@pacbell.net]
Sent: Thursday, August 27, 2009 10:08 PM
To: Troy Kisky
Cc: akpm@linux-foundation.org; dwmw2@infradead.org; linux-mtd@lists.infradead.org; Narnakaje, Snehaprabha; Paulraj, Sandeep; tglx@linutronix.de
Subject: Re: [patch 3/3] mtd-nand: DaVinci: Add 4-bit ECC support for large page NAND chips

On Friday 07 August 2009, Troy Kisky wrote:
> > +static struct nand_ecclayout hwecc4_2048 __initconst = {
> > + ...
> > + .oobfree = {
> > + /* 1 byte at offset 0 holds manufacturer badblock marker */
> > + {.offset = 1, .length = 23, },
>
> I thought Sneha Narnakaje was going to change offset = 2, length = 22 ?

Not clear why; this is only for 8-bit NAND, which (right?)
only uses single byte manufacturer badblock markers ...

Will a TI person be updating U-Boot? Please? :)
During the U-Boot v2009.10 window, which opens up
in a couple days...

- Dave