Re: Re :Re: [Help] SST39VF6401B Support

[Wolfram Sang <w.sang@pengutronix.de>]

[-- Attachment #1: Type: text/plain, Size: 1509 bytes --]

Hi,

On Sat, Oct 16, 2010 at 03:08:46PM +0800, yidong zhang wrote:
> hi
> 
> >Just to apply the patch and see what happens. The most important part
> >of this patch is:
> >
> >Please refer to the data sheets Table 6:
> >39VF6401B data sheet http://www.sst.com/downloads/datasheet/S71288.pdf
> >39VF6401 data sheet http://www.sst.com/downloads/datasheet/S71223-03.pdf
> >
> >The difference in the 6th bus write cycle. 39VF6401B uses 0x50 and
> >39VF6401 uses 0x30.
> >
> >Without this even if the chip gets detected you cannot write to it.
> >
> >I haven't look at this since my try to submit this patch, so I don't
> >know how to fix the stuff for cfi_probe.
> 
>  Recently, i use the 39VF6401B flash, and i apply your patch. The chip
> can be get detected. But when i erase one sector, it use 0x30 to erase
> one block. The size of a block is much bigger than a sector as we
> know.So i use the JEDEC probe to detect the flash. And i make the
> erase size to one block-erase size. And it works fine. So i think
> the  chip(39VF6401B)  should not be CFI compliant, maybe the  JEDEC
> mode is better.

Please have a look at cfi_cmdset_0002.c, especially the table
cfi_nopri_fixup_table. Without verifying the details, I assume you just have to
add the IDs there and then you can have CFI.

Kind regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]