From: Shmulik Ladkani <shmulik.ladkani@gmail.com>
To: Mike Dunn <mikedunn@newsguy.com>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>,
Ivan Djelic <ivan.djelic@parrot.com>,
Ricard Wanderlof <ricard.wanderlof@axis.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
Subject: Re: [PATCH 0/3] MTD: Change meaning of -EUCLEAN return code on reads
Date: Fri, 16 Mar 2012 23:54:24 +0200 [thread overview]
Message-ID: <20120316235424.60a62ed0@halley> (raw)
In-Reply-To: <4F636964.3030904@newsguy.com>
Hi Mike,
On Fri, 16 Mar 2012 09:25:08 -0700 Mike Dunn <mikedunn@newsguy.com> wrote:
> Maybe my (admittedly limited) understanding of the physical nature of NAND flash
> is flawed. I assumed that a writesize region (i.e., a NAND page for our
> purposes) is the most elemental unit wrt physical wear, regardless of whether or
> not ecc is caclulated once for the whole page or incrementally in steps.
Bit-flips may occur at a per-cell basis, even on the OOB cells, as a
result of program-disturb, charge-loss, or cell ware-out causing read
sensing errors.
> But you're sayimg my assumption is incorrect. So each ecc-sized area within a
> page is physically distinct and must be considered in isolation?
There's no "physical" distinction, in the sense that cells are separated
in the device or alike.
Simply, the ECC algorithm is independently calculated over several
portions of the page.
But that's not a must: suppose X bits per Y bytes ECC is required; you
may use a 2X / 2Y ECC and acheive similar intergrity and endurance
statistical characteristics.
For your purposes, the question whether the cleaning decision should be
according to the ecc step level, is dependent of how you define
"a dangerously high number of bit errors".
Lets continue with Ivan's example (2KiB page, 4 eccsteps, 512 bytes
each step, strength 4bits/512bytes).
Suppose the first ECC portion has 4 bit errors, the other 3 portions
have none.
If, for example, several read operations later, a new bitflip is
intorduced within the first portion, leading to 5 bit errors.
Obviously, the ECC algorithm is now unable to correct this portion,
meaning, the buffer is corrupt - which also means the entire page data
read is corrupt. The nand infrastructure would return -EBADMSG - and you
had just 5 bit errors over the entire page.
So question is, would you consider 4 bit errors in the first ECC portion
to be "a dangerously high number of bit errors" as what's reported to
the MTD users?
If so, then yes, the cleaning decision should be according to the ecc
step level, not at the page reading level.
Regards,
Shmulik
next prev parent reply other threads:[~2012-03-16 21:54 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-15 17:25 [PATCH 0/3] MTD: Change meaning of -EUCLEAN return code on reads Mike Dunn
2012-03-15 17:25 ` [PATCH 1/3] MTD: expose ecc_strength through sysfs Mike Dunn
2012-03-15 17:25 ` [PATCH 2/3] MTD: bitflip_threshold added to mtd_info and sysfs Mike Dunn
2012-03-16 16:31 ` Ivan Djelic
2012-03-15 17:25 ` [PATCH 3/3] MTD: drivers return max_bitflips, mtd returns -EUCLEAN Mike Dunn
2012-03-16 11:19 ` [PATCH 0/3] MTD: Change meaning of -EUCLEAN return code on reads Ivan Djelic
2012-03-16 12:49 ` Artem Bityutskiy
2012-03-16 16:30 ` Mike Dunn
2012-03-16 16:25 ` Mike Dunn
2012-03-16 18:43 ` Ivan Djelic
2012-03-17 20:18 ` Mike Dunn
2012-03-18 8:00 ` Shmulik Ladkani
2012-03-19 8:50 ` Matthieu CASTET
2012-03-19 9:29 ` Shmulik Ladkani
2012-03-19 19:09 ` Mike Dunn
[not found] ` <20120319211835.1073a491@halley>
2012-03-20 1:27 ` Mike Dunn
2012-03-30 14:21 ` Artem Bityutskiy
2012-03-31 2:03 ` Mike Dunn
2012-03-30 14:16 ` Artem Bityutskiy
2012-03-31 1:23 ` Mike Dunn
2012-03-30 14:19 ` Artem Bityutskiy
2012-03-16 21:54 ` Shmulik Ladkani [this message]
2012-03-16 22:57 ` Peter Barada
2012-03-17 21:10 ` Mike Dunn
2012-03-17 20:50 ` Mike Dunn
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