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From: Marek Vasut <marex@denx.de>
To: "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>,
	Brian Norris <computersforpeace@gmail.com>
Subject: N25Q256A 13E40
Date: Mon, 7 Oct 2013 18:24:00 +0200	[thread overview]
Message-ID: <201310071824.01028.marex@denx.de> (raw)

Hi guys!

Let's talk about our favourite chip :) I just got my hands on N25Q256A . Since 
there was quite a flurry of patches for this and similar chips and I got it 
working on a different chip with exactly the same IDs and type, I'd would expect 
linux to work with this one too. Guess what ... ;-)

This particular incarnation of N25Q256A completely ignores the 4-byte ERASE 
(0xdc) command. Apparently, if I look closely, it's N25Q256A 13E40 variant and 
seeing the Note #14 (datasheet page 30 / below Table 18. Command set), quoting:

14.This command is only for part numbers N25Q256A83ESF40x and N25Q256A83E1240x.

they are not supported on this part. Someone surely did some hard thinking 
inventing such a crappy part. I can surely cook a patch, but I wonder what 
direction we should take here. We can switch this chip into 4-byte mode by 
0xb7/0xe9 opcodes, which would in turn break BootROMs which depend on the SPI 
NOR to be in 3-byte mode upon reboot. We can program the BAR register before 
erase, which will do the same.

Sigh, if you have any idea, that'd be nice to hear.

Thanks!

             reply	other threads:[~2013-10-07 16:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-07 16:24 Marek Vasut [this message]
2013-10-09  1:05 ` N25Q256A 13E40 Brian Norris
2013-10-09 10:14   ` Marek Vasut
2013-10-09 21:44     ` Brian Norris
2013-10-12  1:17       ` Marek Vasut
2013-10-15 17:22         ` Brian Norris

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