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Date: Mon, 18 Nov 2013 09:33:14 -0800
From: Brian Norris <computersforpeace@gmail.com>
To: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Subject: Re: [PATCH] mtd: nand: pxa3xx: make ECC configuration checks more
 explicit
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On Sun, Nov 17, 2013 at 01:57:05AM -0300, Ezequiel Garcia wrote:
> On Thu, Nov 14, 2013 at 03:18:28PM -0800, Brian Norris wrote:
> > The Armada BCH configuration in this driver uses one of the two
> > following ECC schemes:
> > 
> >  16-bit correction per 2048 bytes
> >  16-bit correction per 1024 bytes
> > 
> > These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit
> > per 512-bytes (respectively) minimum correctability requirements of many
> > common NAND.
> > 
> > The current code only checks for the required strength (4-bit or 8-bit)
> > without checking the ECC step size that is associated with that strength
> > (and simply assumes it is 512). While that is often a safe assumption to
> > make, let's make it explicit, since we have that information.
> > 
> > Signed-off-by: Brian Norris <computersforpeace@gmail.com>
> 
> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

Pushed to l2-mtd.git/next.

Brian