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Date: Thu, 5 Dec 2013 20:06:18 +0100
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: "Gupta, Pekon" <pekon@ti.com>
Subject: Re: OMAP3 NAND ECC selection
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Dear Gupta, Pekon,

On Thu, 5 Dec 2013 19:02:22 +0000, Gupta, Pekon wrote:

> >From: Ezequiel Garcia [mailto:ezequiel.garcia@free-electrons.com]
> [...]
> >AFAIK, there's no hardware limitation that would prevent us from setting
> >a per-partition ECC, keep in mind this effort is not reduced to make
> >devicetree accept ECC on the partitions.
> >
> I had some reservations in doing so.. (as mentioned in previous email also [2])
> I would rather like to understand long term benefits of such implementation.

The long term benefits is simply to properly handle the hardware
constraints. We have hardware platforms were parts of the NAND *MUST*
use 1-bit ECC to be compatible with the ROM code, and other parts of
the NAND *MUST* use stronger 4-bits or 8-bits ECC to comply with the
NAND requirements.

Isn't handling hardware constraints properly not a sufficient
motivation for doing something?

> Also, any constrain due to ROM code, or upgrading from remote can be
> handled using various alternative approaches like [a] and [b].

And you're not realizing that these solutions are ugly and impractical?

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com