* Coping with multibit ECC flashes in UBI
@ 2013-12-06 9:24 Ricard Wanderlof
2013-12-06 11:11 ` Matthieu CASTET
0 siblings, 1 reply; 2+ messages in thread
From: Ricard Wanderlof @ 2013-12-06 9:24 UTC (permalink / raw)
To: Linux mtd
There have been SLC NAND flashes around for a while which according to
their data sheets require 4 or even 8 bit ECC (usually BCH). Traditionally
this was only the case for MLC NAND, with SLC only requiring single-bit
ECC (Hamming), and even then, bit flips were very rare.
For flashes that require multibit ECC, it's common to have single bits
which flip fairly quickly after having been written. Thus, the current
scheme in UBI of rewriting a flash block when an 'ECC corrected' status
has been returned during a read would quickly wear out certain blocks.
I seem to recall there being a discussion like a year ago about
introducing a threshold for the number of corrected bits in a page before
the containing block was rewritten, but I don't know what became of that.
Anyone who was more involved remember more?
(I was going to search the list archives, but at least the page
http://lists.infradead.org/pipermail/linux-mtd/ has no search function).
/Ricard
--
Ricard Wolf Wanderlöf ricardw(at)axis.com
Axis Communications AB, Lund, Sweden www.axis.com
Phone +46 46 272 2016 Fax +46 46 13 61 30
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: Coping with multibit ECC flashes in UBI
2013-12-06 9:24 Coping with multibit ECC flashes in UBI Ricard Wanderlof
@ 2013-12-06 11:11 ` Matthieu CASTET
0 siblings, 0 replies; 2+ messages in thread
From: Matthieu CASTET @ 2013-12-06 11:11 UTC (permalink / raw)
To: Ricard Wanderlof; +Cc: Linux mtd
Le Fri, 6 Dec 2013 10:24:17 +0100,
Ricard Wanderlof <ricard.wanderlof@axis.com> a écrit :
>
> There have been SLC NAND flashes around for a while which according
> to their data sheets require 4 or even 8 bit ECC (usually BCH).
> Traditionally this was only the case for MLC NAND, with SLC only
> requiring single-bit ECC (Hamming), and even then, bit flips were
> very rare.
>
> For flashes that require multibit ECC, it's common to have single
> bits which flip fairly quickly after having been written. Thus, the
> current scheme in UBI of rewriting a flash block when an 'ECC
> corrected' status has been returned during a read would quickly wear
> out certain blocks.
>
> I seem to recall there being a discussion like a year ago about
> introducing a threshold for the number of corrected bits in a page
> before the containing block was rewritten, but I don't know what
> became of that. Anyone who was more involved remember more?
>
In mtd there is now a bitflip_threshold.
Check commit d062d4ede877fcd2ecc4c6262abad09a6f32950a
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2013-12-06 11:12 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-12-06 9:24 Coping with multibit ECC flashes in UBI Ricard Wanderlof
2013-12-06 11:11 ` Matthieu CASTET
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).