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From: Marek Vasut <marex@denx.de>
To: linux-mtd@lists.infradead.org,
 chuck@mds.com
Subject: Re: [PATCH] Check flag status register for Micron n25q512a
Date: Sun, 2 Mar 2014 15:42:09 +0100
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On Sunday, March 02, 2014 at 06:28:26 AM, Chuck Peplinski wrote:
> Sorry about top posting.

You are sorry, yet you did it again :-(

> I am also using this n25q512.  My working code includes a fix similar to
> what Song posted.  I don't consider it elegant.  The problem is that
> this 25q512 apparently behaves in a unique fashion.  If you read the
> status register instead of the flag status register, reads work but
> erases and writes fail.  I know this from a couple of days of
> debugging.

So does the SR and FSR not toggle the bit 7 at the same time or what ?

> You must respond to the flag status register.

What do you mean by "respond" ?

> Yes, this is
> different from every other part.
> 
> Some possible solutions are:
> - hard code support for this device, as Song did.
> - add some other abstraction that affects support for every other part.
> I leave the decision to you, but neither sounds very pretty.
> 
>      Chuck
> 
> On 3/1/2014 1:22 PM, Marek Vasut wrote:
> > To me, it looks like FSR bit 7 and SR bit 7 should toggle exactly at the
> > same time and exactly for the same events. Can you try for example
> > reading them both and checking that the bit 7 really toggles at
> > different times please?
> 
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Best regards,
Marek Vasut