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Date: Mon, 31 Mar 2014 21:45:22 +0200
From: Gerhard Sittig <gsi@denx.de>
To: David Mosberger <davidm@egauge.net>
Subject: Re: [REV3] mtd: nand: Prepare for Micron on-die ECC controller
 support.
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On Mon, 2014-03-31 at 12:33 -0600, David Mosberger wrote:
> 
> On Sat, Mar 29, 2014 at 7:16 AM, Gerhard Sittig <gsi@denx.de> wrote:
> 
> > so the additional buffers only get allocated when upon
> > identification the on-die-ECC feature already is enabled?
> 
> Yes.
> 
> > not
> > when it's supported, and might get enabled at any later point in
> > time?
> 
> There is no way to switch ECC mode later on, is there?

Isn't there the ONFI SETFEATURE request?  And don't you use this
very request to disable and enable chip internal ECC support, to
get the raw (uncorrected) bits after bitflips were detected?  So
I understand that there is support to enable this mode at will,
and we already have (or will have) code to do so.

If we consider disabling on-die-ECC support when we find it
enabled and know it's not what the user wants to run, then the
next logical step might be to support enabling this feature if
the user wants it and the chip doesn't have it enabled at this
point in time.

So I guess the buffers should get allocated as soon as the chip
supports on-die-ECC.  (While the allocation should only get
introduced in the phase where the raw-read and bitflip count gets
added.)


virtually yours
Gerhard Sittig
-- 
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