From: Brian Norris <computersforpeace@gmail.com>
To: Aaron Sierra <asierra@xes-inc.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-mtd@lists.infradead.org,
Scott Wood <scottwood@freescale.com>,
David Woodhouse <dwmw2@infradead.org>,
Prabhakar Kushwaha <prabhakar@freescale.com>
Subject: Re: [PATCH v3] fsl_ifc: Support all 8 IFC chip selects
Date: Wed, 5 Nov 2014 14:54:51 -0800 [thread overview]
Message-ID: <20141105225451.GZ23619@ld-irv-0074> (raw)
In-Reply-To: <264587069.465984.1409095113566.JavaMail.zimbra@xes-inc.com>
On Tue, Aug 26, 2014 at 06:18:33PM -0500, Aaron Sierra wrote:
> Freescale's QorIQ T Series processors support 8 IFC chip selects
> within a memory map backward compatible with previous P Series
> processors which supported only 4 chip selects.
>
> Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
> ---
> Note: v1 and v2 patches were submitted to Linux PPC mailing list
>
> v3: * IFC version register read only once
> * fsl_ifc_version and fsl_ifc_bank_count inline functions replaced
> by version and banks members of struct fsl_ifc_ctrl
> * IFC version print moved from fsl_ifc_nand.c to fsl_ifc.c
Pushed to l2-mtd.git.
Brian
prev parent reply other threads:[~2014-11-05 22:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1560704347.463292.1409093361997.JavaMail.zimbra@xes-inc.com>
2014-08-26 23:18 ` [PATCH v3] fsl_ifc: Support all 8 IFC chip selects Aaron Sierra
2014-08-26 23:21 ` Scott Wood
2014-11-05 22:54 ` Brian Norris [this message]
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