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Date: Mon, 5 Jan 2015 12:47:04 -0800
From: Brian Norris <computersforpeace@gmail.com>
To: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Subject: Re: [PATCH 4/6] mtd: Introduce SPI NAND framework
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On Mon, Dec 22, 2014 at 12:44:23PM -0300, Ezequiel Garcia wrote:
> On 12/22/2014 01:34 AM, Qi Wang 王起 (qiwang) wrote:
> >> +/*
> >> + * Wait until the status register busy bit is cleared.
> >> + * Returns a negatie errno on error or time out, and a non-negative
> >> +status
> >> + * value if the device is ready.
> >> + */
> >> +static int spi_nand_wait_till_ready(struct spi_nand *snand) {
> >> +	unsigned long deadline = jiffies + msecs_to_jiffies(100);
> > 
> > 100ms will be applied to all operation, but I think it would be more
> > make sense to use different timeout value for different operation, 
> > just like Parallel NAND as below:
> > "
> 
> Yes, indeed. You are right. Now we need to find out the appropriate
> value in each case. Any suggestions?

Isn't the value of 'deadline' only important for the uncommon case of a
misbehaving flash? If so, I don't think it's too important to tune it to
be as small as possible.

> > static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
> > {
> > 
> > 	int status, state = chip->state;
> > 	unsigned long timeo = (state == FL_ERASING ? 400 : 20);
> > "	

Brian