Re: RFC: detect and manage power cut on MLC NAND

[Boris Brezillon <boris.brezillon@free-electrons.com>]

Hello Jeff,

I'm joining the discussion to ask more questions about MLC NANDs ;-).

Could you tell us more about how block wear impact the voltage level
stored in NAND cells.

1/ Are all pages in a block impacted the same way ?
2/ Is wear more likely to induce voltage increase, voltage decrease
   or is it unpredictable ?
3/ Is it possible to have more than one working voltage threshold
   (read-retry mode): I did some testing on my Hynix chip (I know you
   work for Micron but that's the only MLC chip I have :-)), and I
   managed to get less bitflips by trying another read-retry mode even
   if the previous one was allowing me to successfully fix existing
   bitflips.
4/ Do you have any numbers/statistics that could
   help us choose the more appropriate read-retry mode according to the
   number of P/E cycles ?
5/ Any other things you'd like to share regarding read-retry ?


Apart from that, we're currently trying to find the most appropriate
way to deal with paired pages, and this sounds rather complicated.
The current idea is to expose paired pages information up to the UBIFS
layer, and let UBIFS decide when it should stop writing on pages paired
with already written pages.
Moreover, we have a few pages we need to protect (UBI metadata: EC and
VID headers) in order to keep UBI/UBIFS consistent.
Do you have anything to share on this topic (ideas, solutions we should
consider, constraints we're not aware of, ...)


Thanks for your valuable information.

Best Regards,

Boris

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com