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Date: Tue, 7 Apr 2015 13:19:28 +0200
From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Andrea Scian <rnd4@dave-tech.it>
Subject: Re: [MLC NAND]: data pattern sensivity
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Hi,

On Tue, 07 Apr 2015 12:31:10 +0200
Andrea Scian <rnd4@dave-tech.it> wrote:

> Il 03/04/2015 19:20, Jeff Lauruhn (jlauruhn) ha scritto:
> > I'm always glad to help out. I'm not sure I quite understand the meaning of "data pattern sensivity", but when I read it seem related to ECC code word size and Cyclicdesign.com is a good resource and in particular http://cyclicdesign.com/whitepapers/Cyclic_Design_NAND_ECC.pdf.  
> 
> Thanks for pointing out the whitepaper

I haven't read this paper yet, but according to the title I doubt it is
related to the "repeated/systematic data pattern" issue.

> 
> > If I'm off track let me know and I will keep looking.
> 
> I don't really know, but, IIUC, is something related to NAND technology
> and its impact is dependent from the specific MLC implementation.
> For sure Boris can help us in have a better understanding of this issue :-)

Actually this problem was mentioned in the Micron document I pointed
out in a previous thread ([1] page 14).
I also found a paper describing the benefit of data scrambling on MLC
chips [2].

Best Regards,

Boris

[1]http://www.bswd.com/FMS09/FMS09-T2A-Grunzke.pdf
[2]http://soc.yonsei.ac.kr/Abstract/International_journal/pdf/106_Data%20Randomization%20Scheme%20for%20Endurance%20Enhancement%20and%20Interference%20Mitigation%20of%20Multilevel%20Flash%20Memory%20Devices.pdf

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com