From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Andrea Scian <rnd4@dave-tech.it>
Cc: "Jeff Lauruhn \(jlauruhn\)" <jlauruhn@micron.com>,
mtd_mailinglist <linux-mtd@lists.infradead.org>
Subject: Re: [MLC NAND]: data pattern sensivity
Date: Tue, 7 Apr 2015 17:08:33 +0200 [thread overview]
Message-ID: <20150407170833.4726f3b9@bbrezillon> (raw)
In-Reply-To: <5523D9D5.1020109@dave-tech.it>
On Tue, 07 Apr 2015 15:21:25 +0200
Andrea Scian <rnd4@dave-tech.it> wrote:
> Thanks for linking this again.
> I think that Jeff can help us in understanding this further.
> The documents is pretty old (2009) and is about TLC only.
> Does it mean that MLC are less (or not at all) affected by this issue?
Some MLC chips require a randomization step: take a look at this
datasheet [1], page 21:
"Users are required to employ randomizer function in the NAND
controller to meet target endurance of the device."
[1]http://www.100y.com.tw/pdf_file/37-SAMSUNG-K9GBG08U0A-SCB0.pdf
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2015-04-07 15:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-03 9:46 [MLC NAND]: data pattern sensivity Andrea Scian
2015-04-03 17:20 ` Jeff Lauruhn (jlauruhn)
2015-04-07 10:31 ` Andrea Scian
2015-04-07 11:19 ` Boris Brezillon
2015-04-07 13:21 ` Andrea Scian
2015-04-07 15:08 ` Boris Brezillon [this message]
2015-04-07 17:45 ` Jeff Lauruhn (jlauruhn)
2015-04-09 20:19 ` Andrea Scian
[not found] <mailman.1.1428433201.16973.linux-mtd@lists.infradead.org>
2015-04-10 2:52 ` Bean Huo 霍斌斌 (beanhuo)
-- strict thread matches above, loose matches on Subject: below --
2015-04-10 8:27 Qi Wang 王起 (qiwang)
2015-04-10 9:30 ` Andrea Scian
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