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Date: Mon, 20 Apr 2015 15:42:26 +0300
From: Baruch Siach <baruch@tkos.co.il>
To: Ricard Wanderlof <ricard.wanderlof@axis.com>
Subject: Re: i.MX25 NFC with 8 bit ecc strength
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Hi Ricard,

On Mon, Apr 20, 2015 at 02:19:43PM +0200, Ricard Wanderlof wrote:
> On Mon, 20 Apr 2015, Baruch Siach wrote:
> > I'm trying to get nand_ecclayout right on i.MX25 with the Micron 
> > MT29F8G08ABABA (page size: 4096, oob size: 224). The large OOB size allows 
> > using hardware ecc strength of 8bit per ecc step (512 bytes). The mxc_nand 
> > driver code (get_eccsize()) and the reference manual seems to indicate 
> > that enabling 8 bit ecc mode requires 26 oob bytes per ecc step.
> 
> Note sure if these really is relevant to this thread, but using BCH, 8 bit 
> error correction per 512 byte ECC step requires 13 bytes of ECC codes per 
> ECC step. (Depending on other factors, this will actually fit nicely even 
> in a 64 byte OOB).

The i.MX25 NFC hardware uses Reed-Solomon ECC, according to the documentation, 
and needs 18 ECC bytes per 512 step. But even with 13 bytes per step, you'll 
need at least 104 (13*8) OOB bytes for a 4K page.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
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