From: Viresh Kumar <viresh.kumar@linaro.org>
To: Stefan Roese <sr@denx.de>
Cc: linux-mtd@lists.infradead.org,
Linus Walleij <linus.walleij@linaro.org>,
Brian Norris <computersforpeace@gmail.com>
Subject: Re: [PATCH] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
Date: Wed, 2 Sep 2015 16:42:06 +0530 [thread overview]
Message-ID: <20150902111206.GF26744@linux> (raw)
In-Reply-To: <1441187581-12928-1-git-send-email-sr@denx.de>
On 02-09-15, 11:53, Stefan Roese wrote:
> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
> be used by boards equipped with a NAND chip that requires 4-bit ECC
> strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
>
> To enable SW BCH4, you need to specify this in your nand controller
> DT node:
>
> nand-ecc-mode = "soft_bch";
>
> Tested on a custom SPEAr600 board.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> ---
> drivers/mtd/nand/fsmc_nand.c | 72 ++++++++++++++++++++++++++++++++------------
> include/linux/mtd/fsmc.h | 2 ++
> 2 files changed, 54 insertions(+), 20 deletions(-)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
next prev parent reply other threads:[~2015-09-02 11:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 9:53 [PATCH] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 Stefan Roese
2015-09-02 11:12 ` Viresh Kumar [this message]
2015-09-29 0:21 ` Brian Norris
2015-10-02 10:33 ` Stefan Roese
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