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Date: Fri, 23 Oct 2015 18:15:47 -0700
From: Brian Norris <computersforpeace@gmail.com>
To: Ray Jui <rjui@broadcom.com>
Cc: Clay McClure <clay@daemons.net>, linux-mtd@lists.infradead.org,
 Florian Fainelli <f.fainelli@gmail.com>,
 Scott Branden <sbranden@broadcom.com>,
 bcm-kernel-feedback-list@broadcom.com
Subject: Re: [PATCH] mtd: brcmnand: Fix NAND_CMD_PARAM byte order
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On Fri, Oct 23, 2015 at 06:12:19PM -0700, Brian Norris wrote:
> On Fri, Oct 23, 2015 at 05:48:11PM -0700, Ray Jui wrote:
> > If so, then should the logic here be the following?
> > 
> > ret = cpu_to_le32(ctrl->flash_cache[offs >> 2]) >> ((offs & 0x03) << 3);
> 
> I guess so, but that's getting even uglier, not prettier.

Sorry, I misread. No, that will break brcmstb too. The logic as-is is
tested and works for little endian BCM7xxx MIPS and ARM, regardless of
theory. You'll need to figure out the quirks of why/how it's really
*supposed* to work (and then to write good code around that) to get more
platforms to work with it.

Brian