From: Brian Norris <computersforpeace@gmail.com>
To: Han Xu <b45815@freescale.com>
Cc: shijie.huang@arm.com, dwmw2@infradead.org,
boris.brezillon@free-electrons.com, fabio.estevam@freescale.com,
hofrat@osadl.org, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org, vinod.koul@intel.com,
dan.j.williams@intel.com, dmaengine@vger.kernel.org
Subject: Re: [PATCH v8 4/7] mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NAND
Date: Sat, 23 Jan 2016 14:56:46 -0800 [thread overview]
Message-ID: <20160123225646.GH24744@localhost> (raw)
In-Reply-To: <1449096466-18064-5-git-send-email-b45815@freescale.com>
On Wed, Dec 02, 2015 at 04:47:43PM -0600, Han Xu wrote:
> By default NAND driver will choose the highest ecc strength that oob
> could contain, in this case, for some 8K+744 NAND flash, the ecc
> strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability
> (40bit).
>
> This patch allows the NAND driver try to use minimum required ecc
> strength if it failed to use the highest ecc, even without explicitly
> claiming "fsl,use-minimum-ecc" in dts.
>
> Signed-off-by: Han Xu <b45815@freescale.com>
Pushed this one to l2-mtd.git/next too.
Would it help to implement support for the "nand-ecc-step-size" and
"nand-ecc-strength" properties sometime? That would be more
maintainable, as it's more specific. What if you need a little stronger
than the minimum ECC? You also are relying on not changing the default
behavior of the driver, for the "legacy" ECC calculation still. That
ties your hands a bit.
Brian
next prev parent reply other threads:[~2016-01-23 22:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-02 22:47 [PATCH v8 0/7] mtd: nand: gpmi: gpmi-nand DSM and bitflip support Han Xu
2015-12-02 22:47 ` [PATCH v8 1/7] mtd: nand: gpmi: add gpmi dsm supend/resume support Han Xu
2016-01-23 22:54 ` Brian Norris
2015-12-02 22:47 ` [PATCH v8 2/7] dmaengine: mxs: APBH DMA supports deep sleep mode Han Xu
2015-12-05 11:10 ` Vinod Koul
2015-12-02 22:47 ` [PATCH v8 3/7] dmaengine: mxs: add i.MX7D APBH DMA support Han Xu
2015-12-05 11:12 ` Vinod Koul
2015-12-02 22:47 ` [PATCH v8 4/7] mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NAND Han Xu
2015-12-17 2:10 ` Huang Shijie
2016-01-23 22:56 ` Brian Norris [this message]
2015-12-02 22:47 ` [PATCH v8 5/7] mtd: nand: gpmi: add GPMI NAND support for i.MX7D Han Xu
2015-12-17 2:12 ` Huang Shijie
2016-01-23 22:58 ` Brian Norris
2015-12-02 22:47 ` [PATCH v8 6/7] mtd: nand: gpmi: correct bitflip for erased NAND page Han Xu
2015-12-17 2:11 ` Huang Shijie
2016-01-23 23:01 ` Brian Norris
2016-02-02 13:28 ` Markus Pargmann
2016-02-17 22:36 ` Han Xu
2015-12-02 22:47 ` [PATCH v8 7/7] mtd: nand: gpmi: support NAND on i.MX6UL Han Xu
2015-12-17 2:07 ` Huang Shijie
2016-01-23 23:03 ` Brian Norris
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160123225646.GH24744@localhost \
--to=computersforpeace@gmail.com \
--cc=b45815@freescale.com \
--cc=boris.brezillon@free-electrons.com \
--cc=dan.j.williams@intel.com \
--cc=dmaengine@vger.kernel.org \
--cc=dwmw2@infradead.org \
--cc=fabio.estevam@freescale.com \
--cc=hofrat@osadl.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=shijie.huang@arm.com \
--cc=vinod.koul@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).