Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Boris Brezillon]

On Tue, 1 Mar 2016 14:47:21 +0000
Bean Huo 霍斌斌 (beanhuo) <beanhuo@micron.com> wrote:

> Hi, Andrea and Boris
> This is a historical subject, and talked before. 
> From our field issues, 8 bits of bad block mark for MLC NAND is not reasonable.
> Because of bitflip on bad block mark, regard one good block as a bad block is common
> Issue. Especially first time boot after reflow. The solution is modified this value to 4 for MLC
> NAND by hand, and the factory BB mark is “0x00”.
> I think, 4 bits for MLC NAND make sense.


I'm tempted to say "let's start with this value and see what happens in
real world". If we want to be a bit more conservative we could decide
to chose 2, which should address most problems too (during my tests, I
never seen such a huge concentration of bitflips in the same byte).

Brian, Andrea, what do you think?

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Andrea Scian]

Il 09/03/2016 15:26, Boris Brezillon ha scritto:
> On Tue, 1 Mar 2016 14:47:21 +0000
> Bean Huo 霍斌斌 (beanhuo) <beanhuo@micron.com> wrote:
>
>> Hi, Andrea and Boris
>> This is a historical subject, and talked before.
>>  From our field issues, 8 bits of bad block mark for MLC NAND is not reasonable.
>> Because of bitflip on bad block mark, regard one good block as a bad block is common
>> Issue. Especially first time boot after reflow. The solution is modified this value to 4 for MLC
>> NAND by hand, and the factory BB mark is “0x00”.
>> I think, 4 bits for MLC NAND make sense.
>
>
> I'm tempted to say "let's start with this value and see what happens in
> real world". If we want to be a bit more conservative we could decide
> to chose 2, which should address most problems too (during my tests, I
> never seen such a huge concentration of bitflips in the same byte).
>
> Brian, Andrea, what do you think?
>

I'm currently using 4 on my custom kernel.
On all datasheet I've seen factory bad block marker is 0x00 and the same 
is (AFAIK) used by MTD to mark bad blocks.

Kind Regards,

-- 

Andrea SCIAN

DAVE Embedded Systems

RE: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Bean Huo 霍斌斌 (beanhuo)]

> >> Hi, Andrea and Boris
> >> This is a historical subject, and talked before.
> >>  From our field issues, 8 bits of bad block mark for MLC NAND is not
> reasonable.
> >> Because of bitflip on bad block mark, regard one good block as a bad
> >> block is common Issue. Especially first time boot after reflow. The
> >> solution is modified this value to 4 for MLC NAND by hand, and the factory
> BB mark is “0x00”.
> >> I think, 4 bits for MLC NAND make sense.
> >
> >
> > I'm tempted to say "let's start with this value and see what happens
> > in real world". If we want to be a bit more conservative we could
> > decide to chose 2, which should address most problems too (during my
> > tests, I never seen such a huge concentration of bitflips in the same byte).
> >
> > Brian, Andrea, what do you think?
> >
> 
> I'm currently using 4 on my custom kernel.
> On all datasheet I've seen factory bad block marker is 0x00 and the same is
> (AFAIK) used by MTD to mark bad blocks.
> 
> Kind Regards,
> 
> --
> 
> Andrea SCIAN
> 
> DAVE Embedded Systems
Micron factory bad block marker of all NAND is 0x00.
But for good bad, after reflow, most good block will be
made mistake of think bad block just Because of bitflips 
on marker bytes. I want to clarify this is first time boot.
Currently no bad block table.

[PATCH 0/2] Use badblockbits-like approach in nand_bbt.c

[rnd4]

Hi all,

I'm currenlty working with an MLC NAND (MT29F32G08CBACAWP) on a iMX6 based
platform (kernel 3.10.17).
The first problem I have is about badblock detection. I experienced a lot of bit
flips on badblock marker (some of them probalbly due misuse, e.g. powercut).

By looking into the MDT code, I've found that inside nand_base.c there's support
for badblockbits feature, which, for short, allow to tolerate 1 or more bitflip
when looking for BB.

In my experience usually the marker is 0x00 for bad blocks and 0xFF for good one
(at least this is true for my current component).

Unfortunately this approach is not used into BBT code (nand_bbt.c) and thus I have
a lot of false positive BB.

With the following patches I try to add badblockbits-like approach to nand_bbt.c
code.

The first patch is optional and configure badblockbits depending on SLC vs MLC NAND.

The second patch implements the badblockbits approach into BBT scan.
Please note that this is not usually enough, because many NAND controller override
nand_bbt_descr and thus requires changes also the the specific controller driver.

The patch has been made in collaboration with Boris Brezillon (thank you for you
suggestions Boris).

I tested it on a 3.10.17 kernel, but the second patch applies fine to
v3.10 stable and latest 4.0-rc1 (the first patch needs some changes to apply to this
one).

Feel free to comment it and tell me if something can be done in a better way

Best Regards,

Andrea Scian
DAVE Embedded Systems

[PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[rnd4]

From: Andrea Scian <andrea.scian@dave.eu>

MLC NANDs have more bit flips that SLC. When looking for bad block
marker we have a lot of false positive if we check for the whole byte. To
avoid this tolerate a few (4 here) bit flips for byte.

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
---
 drivers/mtd/nand/nand_base.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dfcd0a5..bdca223 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3315,7 +3315,10 @@ ident_done:
 		chip->chip_shift += 32 - 1;
 	}
 
-	chip->badblockbits = 8;
+	if (nand_is_slc(chip))
+		chip->badblockbits = 8;
+	else
+		chip->badblockbits = 4;
 	chip->erase_cmd = single_erase_cmd;
 
 	/* Do not replace user supplied command function! */
-- 
1.7.9.5

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Boris Brezillon]

Hi Andrea,

On Fri,  6 Mar 2015 13:12:17 +0100
rnd4@dave-tech.it wrote:

> From: Andrea Scian <andrea.scian@dave.eu>
> 
> MLC NANDs have more bit flips that SLC. When looking for bad block
> marker we have a lot of false positive if we check for the whole byte. To
> avoid this tolerate a few (4 here) bit flips for byte.

I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
this value should be chip dependent.
I know there is currently no way to retrieve this information, so here
are two suggestions:

1/ make this value depend on the required NAND ecc strength
(badblockbits = ecc_strength / 10 ?)
2/ let each controller change this value after nand_scan_ident
depending on the detected chip until we find a generic solution to
select this value

Best Regards,

Boris

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Andrea Scian]

Sorry for the later feedback, but unfortunately I had to move to other
stuff before coming back to this topic

Il 15/03/2015 10:07, Boris Brezillon ha scritto:
> Hi Andrea,
> 
> On Fri,  6 Mar 2015 13:12:17 +0100
> rnd4@dave-tech.it wrote:
> 
>> From: Andrea Scian <andrea.scian@dave.eu>
>>
>> MLC NANDs have more bit flips that SLC. When looking for bad block
>> marker we have a lot of false positive if we check for the whole byte. To
>> avoid this tolerate a few (4 here) bit flips for byte.
> 
> I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
> this value should be chip dependent.

I agree

> I know there is currently no way to retrieve this information,

For this reason I just put a hardcoded value.

> so here are two suggestions:
> 
> 1/ make this value depend on the required NAND ecc strength
> (badblockbits = ecc_strength / 10 ?)
> 2/ let each controller change this value after nand_scan_ident
> depending on the detected chip until we find a generic solution to
> select this value

I'll try to figure out how to solve this
Any suggestion is welcome!

Regards,

-- 

Andrea SCIAN

DAVE Embedded Systems

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Andrea Scian]

Dear Bean,

Il 21/07/2015 16:50, Bean Huo 霍斌斌 (beanhuo) ha scritto:
 > Hi,
 > What is status of this patch? I think 4 bits is make sense for all
 > MLC nand,
 > Bit flips on bad block mark should not be regarded as a bad block.
 >

I think that there was something wrong with your email, because I didn't 
see it in MTD ML archives, probably it has been blocked for some reason.

I didn't find a solution to implement Boris suggestions on how to choose 
the bad block bit threshold. In my implementation is still statically 
defined.

However I did some minor changes to the second patch, I'll send it in a 
few minutes.

Any feedback is welcome, of course ;-)

Kind Regards,

Andrea Scian


Il 03/04/2015 14:52, Andrea Scian ha scritto:
>
> Sorry for the later feedback, but unfortunately I had to move to other
> stuff before coming back to this topic
>
> Il 15/03/2015 10:07, Boris Brezillon ha scritto:
>> Hi Andrea,
>>
>> On Fri,  6 Mar 2015 13:12:17 +0100
>> rnd4@dave-tech.it wrote:
>>
>>> From: Andrea Scian <andrea.scian@dave.eu>
>>>
>>> MLC NANDs have more bit flips that SLC. When looking for bad block
>>> marker we have a lot of false positive if we check for the whole byte. To
>>> avoid this tolerate a few (4 here) bit flips for byte.
>>
>> I'm not sure sure we want to accept 4 bitflips for all MLC NANDs. IMHO
>> this value should be chip dependent.
>
> I agree
>
>> I know there is currently no way to retrieve this information,
>
> For this reason I just put a hardcoded value.
>
>> so here are two suggestions:
>>
>> 1/ make this value depend on the required NAND ecc strength
>> (badblockbits = ecc_strength / 10 ?)
>> 2/ let each controller change this value after nand_scan_ident
>> depending on the detected chip until we find a generic solution to
>> select this value
>
> I'll try to figure out how to solve this
> Any suggestion is welcome!
>
> Regards,
>

-- 

Andrea SCIAN

DAVE Embedded Systems

Re: [PATCH 1/2] mtd: nand: use a lower value for badblockbits when working with MLC NAND

[Brian Norris]

On Thu, Jul 23, 2015 at 11:24:54PM +0200, Andrea Scian wrote:
> Il 21/07/2015 16:50, Bean Huo 霍斌斌 (beanhuo) ha scritto:
> > Hi,
> > What is status of this patch? I think 4 bits is make sense for all
> > MLC nand,
> > Bit flips on bad block mark should not be regarded as a bad block.
> >
> 
> I think that there was something wrong with your email, because I
> didn't see it in MTD ML archives, probably it has been blocked for
> some reason.

X-Bad-Reply: 'Re:' in Subject but no References or In-Reply-To headers

I would let it through the moderation filter, but it would screw with
everybody's threading, and the entire contents are there in the quote
anyway.

Bean: please fix your mailer.

Regards,
Brian