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Date: Wed, 9 Mar 2016 10:50:24 -0800
From: Brian Norris <computersforpeace@gmail.com>
To: Jiancheng Xue <xuejiancheng@huawei.com>
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
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 Binquan Peng <pengbinquan@huawei.com>
Subject: Re: [RESEND PATCH v7] mtd: spi-nor: add hisilicon spi-nor flash
 controller driver
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 <20160307225229.GC55664@google.com> <56DE9A79.30704@huawei.com>
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On Tue, Mar 08, 2016 at 05:25:13PM +0800, Jiancheng Xue wrote:
> On 2016/3/8 6:52, Brian Norris wrote:
> [...]
> >> +static void hisi_spi_nor_dma_transfer(struct spi_nor *nor, u32 start_off,
> >> +		u32 dma_buf, u32 len, u8 op_type)
> > 
> > Does this controller support 64-bit addresses? What if you see LPAE, or
> > an ARM64 CPU? It'd be nice if you don't truncate potentially 64-bit
> > dma_buf down to u32.
> > 
> > Brian
> > 
> No, this controller just supports 32-bit addresses. So I think I have to truncate 64-bit dma_buf. :(

Then you should handle this proactively. Either some kind of WARN_ON and
error condition, or I think dma_set_mask_and_coherent(dev,
DMA_BIT_MASK(32)) should be able to ensure you get addresses in the
appropriate range?

Brian