Re: SPI NAND support in drivers/mtd/spi-nor/spi-nor.c

[Boris Brezillon <boris.brezillon@free-electrons.com>]

+Peter

On Mon, 7 Nov 2016 18:01:15 -0800
Brian Norris <computersforpeace@gmail.com> wrote:

> + others
> 
> On Mon, Nov 07, 2016 at 09:53:34AM +0000, Yao Yuan wrote:
> >    Hi All,  
> 
> Hi Yao,
> 
> I'm not that interested in handling private requests, and this is
> generally informative, so I've added the linux-mtd list, as well as the
> other maintainers.
> 
> Also, when you're ready to send patches, make sure you use plain text
> instead of HTML email.
> 
> >    I’m trying to add the QSPI NAND support in MTD.

Yao, can you sync with Peter who is currently working on a SPI NAND
framework (which would sit in drivers/mtd/nand/spi/).

> > 
> >    But I have reached a junction, could you please take some minutes and
> >    give me some suggestions?
> > 
> > 
> >    You know, we have the QSPI NOR support in
> >    drivers/mtd/spi-nor/spi-nor.c,
> > 
> >    And the QSPI NAND is very similar with QSPI NOR, but the Read, write
> >    and erase is different with SPI-NOR.  
> 
> How similar is the controller hardware? Does your IP support standard
> SPI protocol, or is it specialized for accelerating SPI NAND (e.g.,
> memory-mapped, DMA, etc.)? Does it support SPI NOR?
> 
> >    So I have two ways to add QSPI-NAND:  
> 
> I'll leave your options intact below, but I don't think either of them
> are that good. SPI NOR and SPI NAND are different enough, I doubt that
> we'll get much benefit from using the same framework, unless you happen
> to have IP that's designed for both NOR and NAND, yet doesn't quite do
> traditional SPI.
> 
> Particularly, NAND flash has a lot of issues that NOR flash generally
> does not, around bad block management and wear leveling. Also, there may
> be something to share around identification/ONFI? (Not sure how similar
> the implementations are there.) There's been some prior discussion about
> it, and maybe one of the CC'd people can direct you toward the latest
> opinions, or else you can search the archives youreself ("SPI NAND"
> should turn up several results).
> 
> So the main issues would probably be around abstracting out the
> bad-block-related and chip identification code so you can share code
> with existing (parallel) NAND support. At least, that's what I think
> based on the last time I looked at things, and I think some of the other
> active maintainers had ideas along the same lines.

I'm not sure identification of raw and SPI NAND is working the same
way, but that's true for the BBT. And, as Brian said, you don't interact
with NANDs the same way you do with NORs, so it should IMO stay in
different frameworks.

Now, the remaining question is, how can we share QSPI controller code
between SPI-NOR and SPI-NAND (is it really needed?)?
I guess we could have a drivers/mtd/spi-flash directory containing such
controller drivers, and then each controller would register one or
several SPI-NOR/NAND devices to the spi-nor and spi-nand frameworks.

I'm just guessing here, and I don't know enough about SPI flashes to
have a definitive opinion on this.

Ezequiel, Cyrille, Marek, what's your opinion?

Regards,

Boris