From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cPUBE-00019T-C9 for linux-mtd@lists.infradead.org; Fri, 06 Jan 2017 13:03:39 +0000 Received: by mail-lf0-x244.google.com with SMTP id k62so3253458lfg.0 for ; Fri, 06 Jan 2017 05:03:16 -0800 (PST) From: Marcin Krzeminski To: cyrille.pitchen@atmel.com, marek.vasut@gmail.com, linux-mtd@lists.infradead.org Cc: dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, mar.krzeminski@gmail.com Subject: [PATCH v3 2/2] mtd: spi-nor: Disable chip erase for Micron n25q00. Date: Fri, 6 Jan 2017 14:03:02 +0100 Message-Id: <20170106130302.8074-4-mar.krzeminski@gmail.com> In-Reply-To: <20170106130302.8074-1-mar.krzeminski@gmail.com> References: <20170106130302.8074-1-mar.krzeminski@gmail.com> List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Micron n25q00 are stacked chips, thus do not support chip erase. >>From now spi-nor framework will not send chip erase command, instead use sector at time erase procedure. Signed-off-by: Marcin Krzeminski --- drivers/mtd/spi-nor/spi-nor.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b6656b2..3b416d6 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -950,8 +950,8 @@ static const struct flash_info spi_nor_ids[] = { { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, -- 2.9.3