SW ECC - double bit flip detection on old NAND devices

[Lukasz Majewski <lukma@denx.de>]

Dear All,

I've a problem with pretty old Flash NAND memory (Samsung 128Mx8) [1]

It doesn't support On-Chip ECC - one needs to calculate ECC manually.

The Yaffs2 FS (for this version) uses "1bit correction
ECC" (yaffs_ecc.c). It calculates ECC for 256 bytes -> we have got 22
bits for ECC (rounded up to 3 bytes).

For 2048 bytes page we do have 8 such ECC blocks -> 24 ECC bytes in
total in OOB.

This code (as noted in yaffs_ecc.* header) is able to correct one
single bit flip.

I've also looked into Linux kernel code for SW ECC calculation:

http://elixir.free-electrons.com/linux/latest/source/drivers/mtd/nand/nand_ecc.c#L523

And here it is also explicitly said that we can correct one bit in such
chunk.

Please correct me if I'm wrong but when we have two bit-flips in such
256 bytes chunk, the ECC will be still correct and such obviously
broken page will not be "retired".

What one can do to prevent such situation? 

My idea, if the above holds, would be to implement better ECC scheme as
proposed in "Error Correction Code (ECC) in Micron" doc [2].

Maybe somebody knows better/simpler solution?


Side note: newer NANDs support On-Chip ECC with algorithms allowing
correction of up to 4 bits in 512B chunks of data.


[1] -
http://www.sst-ic.com/File/Seriea/PDF/100923163334f47b2ce6-13b7-43d0-9b8c-ec1c75ca2c6f.pdf
[2] -
https://www.micron.com/~/media/documents/products/technical-note/nand-flash/tn2963_ecc_in_slc_nand.pdf

Best regards,

Lukasz Majewski

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