From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Jan Glauber <jan.glauber@caviumnetworks.com>
Cc: linux-mtd@lists.infradead.org,
Richard Weinberger <richard@nod.at>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Marek Vasut <marek.vasut@gmail.com>,
Cyrille Pitchen <cyrille.pitchen@atmel.com>
Subject: Re: [RFC PATCH 2/2] nand: cavium: Nand flash controller for Cavium ARM64 SOCs
Date: Mon, 15 May 2017 14:35:23 +0200 [thread overview]
Message-ID: <20170515143523.539feaa9@bbrezillon> (raw)
In-Reply-To: <20170515143337.52c49094@bbrezillon>
On Mon, 15 May 2017 14:33:37 +0200
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> Hi Jan,
>
> On Sun, 30 Apr 2017 15:01:00 +0200
> Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
>
> >
> > >
> > > How far are you with the new interface, can you share some code?
> >
> > I started to rework the NAND framework a while ago [1], but never had
> > time to finish it. I think I was too ambitious, so let's try to be
> > pragmatic this time, and focus on one problem at a time.
> >
> > Your problem here is the separation of the CMD/ADDR cycles (done in
> > ->cmdfunc() and/or cmd_ctrl()) and the DATA cycles (done in
> > ->read/write_buf/byte/word()), which complexifies the driver logic.
> >
> > What you should look at is defining a proper nand_operation object
> > (here's my initial definition [2], but you may want/need to remove some
> > fields or add new ones) and add a new ->exec_op() hook to nand_chip
> > taking a nand_operation struct (+ a pointer to the nand_chip, of
> > course).
> >
> > Once you have that, you should patch all accesses from the core to use
> > the new ->exec_op() interface instead of ->cmdfunc() +
> > ->read/write_xx(). Of course, that means providing a compatibility layer
> > for all drivers still implementing ->cmdfunc(), which is probably the
> > trickiest part of the job.
> >
> > You'll have to rework the nand_do_read/write_ops() functions to
> > prevent the separation of the ->cmdfunc() call (done in
> > nand_do_read/write_ops() function) from the data transfer (done in
> > chip->ecc.read/write_page_xxx()).
> >
> > I'll try to come up with an initial/ugly patch to show you the
> > direction, and I'll let you cleanup/massage the implementation ;-).
>
> I finally had time to finish the PoC I had in mind [1], unfortunately I
> didn't have time to provide a reference implementation to show you how
> it is supposed to work from a driver PoV.
One more thing, this is completely untested (only compile-tested), so
you're likely to face bugs when testing it ;-).
next prev parent reply other threads:[~2017-05-15 12:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-27 16:05 [RFC PATCH 0/2] Cavium NAND flash driver Jan Glauber
2017-03-27 16:05 ` [RFC PATCH 1/2] dt-bindings: mtd: Add Cavium SOCs NAND bindings Jan Glauber
2017-03-28 20:20 ` Boris Brezillon
2017-03-28 21:30 ` Jan Glauber
2017-04-03 13:29 ` Rob Herring
2017-04-03 14:38 ` Jan Glauber
2017-04-03 14:47 ` Rob Herring
2017-04-03 16:18 ` Jan Glauber
2017-03-27 16:05 ` [RFC PATCH 2/2] nand: cavium: Nand flash controller for Cavium ARM64 SOCs Jan Glauber
2017-03-29 9:29 ` Boris Brezillon
2017-03-29 10:02 ` Jan Glauber
2017-03-29 13:59 ` Boris Brezillon
2017-04-25 11:26 ` Jan Glauber
2017-04-30 13:01 ` Boris Brezillon
2017-05-15 12:33 ` Boris Brezillon
2017-05-15 12:35 ` Boris Brezillon [this message]
2017-05-19 7:51 ` Boris Brezillon
2017-05-22 11:35 ` Jan Glauber
2017-05-22 11:53 ` Boris Brezillon
2017-05-22 11:44 ` Boris Brezillon
2017-07-20 20:25 ` [RFC PATCH 0/2] Cavium NAND flash driver Karl Beldan
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