From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Mon, 6 Nov 2017 14:24:48 +0100 From: Miquel RAYNAL To: Rob Herring Cc: Andrew Lunn , bcm-kernel-feedback-list@broadcom.com, Boris Brezillon , Brian Norris , Catalin Marinas , Chen-Yu Tsai , Cyrille Pitchen , Daniel Mack , David Woodhouse , devel@driverdev.osuosl.org, devicetree@vger.kernel.org, Ezequiel Garcia , Greg Kroah-Hartman , Gregory Clement , Han Xu , Haojian Zhuang , Jason Cooper , Josh Wu , Kamal Dasu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mtd@lists.infradead.org, Marc Gonzalez , Marek Vasut , Mark Rutland , Masahiro Yamada , Matthias Brugger , Maxime Ripard , Maxim Levitsky , Richard Weinberger , Robert Jarzmik , Russell King , Sebastian Hesselbarth , Stefan Agner , Sylvain Lemieux , Vladimir Zapolskiy , Wenyou Yang , Will Deacon , Thomas Petazzoni , Antoine Tenart , Igor Grinberg , Nadav Haklai , Ofer Heifetz , Neta Zur Hershkovits , Hanna Hawa Subject: Re: [RFC 05/12] dt-bindings: mtd: add Marvell NAND controller documentation Message-ID: <20171106142448.40ca5033@xps13> In-Reply-To: <20171024190433.r5xy25eqdesz7jjs@rob-hp-laptop> References: <20171018143629.29302-1-miquel.raynal@free-electrons.com> <20171018143629.29302-6-miquel.raynal@free-electrons.com> <20171024190433.r5xy25eqdesz7jjs@rob-hp-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Rob, > > +Required properties: > > +C'est faux, t'en a rajout=C3=A9 un y a pas longtps :). > > +Je conseille de mettre =C3=A7a sous forme de liste, genre =20 >=20 > Humm. Oops! >=20 > > + > > +- compatible: can be one of the following: > > + * "marvell,armada-8k-nand-controller" > > + * "marvell,armada370-nand-controller" > > + * "marvell,pxa3xx-nand-controller" > > + * "marvell,armada-8k-nand" (deprecated) > > + * "marvell,armada370-nand" (deprecated) > > + * "marvell,pxa3xx-nand" (deprecated) > > +- reg: shall contain registers location and length for data and > > reg. =20 >=20 > 2 regions? Just one, rephrased. >=20 > > +- #address-cells: shall be set to 1. Encode the nand CS. > > +- #size-cells: shall be set to 0. > > +- interrupts: shall define the nand controller interrupt. > > +- clocks: shall reference nand controller clocks. =20 >=20 > How many clocks? Only one too: "reference the NAND controller clock". >=20 > > +- marvell,system-controller: Set to retrieve the syscon node that > > handles > > + NAND controller related registers (only required with the > > + "marvell,armada-8k-nand[-controller]" compatibles). > > + > > +Optional properties: > > +- dmas: shall reference DMA channel associated to the NAND > > controller. +- dma-names: shall be "rxtx". > > + > > +Optional children nodes: > > +Children nodes represent the available NAND chips. > > + > > +Required properties: > > +- reg: shall contain the native Chip Select ids (0-3) > > +- marvell,rb: shall contain the native Ready/Busy ids (0-1) > > + > > +Optional properties: > > +- marvell,nand-keep-config: orders the driver not to take the > > timings > > + from the core and leaving them completely untouched. Bootloader > > + timings will then be used. > > +- marvell,nand-enable-arbiter: only useful for PXA platforms, will > > + enable bus arbiter between NFC and DFI bus (must be enabled for > > + NFC operation) =20 >=20 > Why do you need this if it must be enabled? That is right, there is no more need for it, also removed it from the driver, just knowing the board with the compatible string is enough. >=20 > > +- nand-on-flash-bbt: speed up the boot process by not discovering > > all > > + the bad blocks at each boot and reading directly an on flash > > table. +- nand-ecc-mode: one of the supported ECC modes ("none", > > "soft", > > + "hw"). If not specified, hardware ECC will be used. > > +- nand-ecc-algo: algorithm to use if previous choice was "soft" > > + ("hamming" or "bch). This property may be added for hardware ECC > > for > > + clarification but will be ignored by the driver because ECC mode > > is > > + chosen depending on the page size and the strength required by > > the > > + NAND chip. This value may be overwritten with the > > nand-ecc-strength > > + property. > > +- nand-ecc-strength: desired ECC strength. > > +- nand-ecc-step-size: indication on the ECC step size. This has no > > + effect and will be ignored by the driver when using hardware > > + ECC. Because Marvell's NAND flash controller does use fixed > > strength > > + (1-bit for Hamming, 16-bit for BCH), the step size will shrink or > > + grown in order to fit the required strength and the value > > + updated. Step sizes are not completely random for all and follow > > + certain patterns described in AN-379, "Marvell SoC NFC ECC". =20 >=20 > For standard properties, just reference nand.txt and add any=20 > constraints. Don't define what the property is again. Ok. >=20 > > + > > +See Documentation/devicetree/bindings/mtd/nand.txt for more > > details on +generic bindings. > > + > > + > > +Example: > > +nand_controller: nand-controller@d0000 { > > + compatible =3D "marvell,armada370-nand-controller"; > > + reg =3D <0xd0000 0x54>; > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + interrupts =3D ; > > + clocks =3D <&coredivclk 0>; > > + status =3D "okay"; =20 >=20 > Don't show status in examples. Ok. >=20 > > + > > + nand@0 { > > + reg =3D <0>; > > + marvell,rb =3D <0>; > > + nand-ecc-mode =3D "hw"; > > + marvell,nand-keep-config; > > + marvell,nand-enable-arbiter; > > + nand-on-flash-bbt; > > + nand-ecc-strength =3D <4>; > > + nand-ecc-step-size =3D <512>; > > + > > + partitions { > > + compatible =3D "fixed-partitions"; > > + #address-cells =3D <1>; > > + #size-cells =3D <1>; > > + > > + partition@0 { > > + label =3D "Rootfs"; > > + reg =3D <0x00000000 0x40000000>; > > + }; > > + }; > > + }; > > +}; > > --=20 > > 2.11.0 > > =20 Thanks for the review, Miqu=C3=A8l