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Sender: Ladislav Michl <ladis@linux-mips.org>
From: Ladislav Michl <ladis@linux-mips.org>
To: Tony Lindgren <tony@atomide.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>,
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Subject: Re: [PATCH v3 5/7] mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA
 implementation
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On Fri, Nov 10, 2017 at 07:24:23AM -0800, Tony Lindgren wrote:
> FYI, the gpio pin for onenand should not be in gpio mode. It should
> be used as external dma request line to automatically trigger new
> transfers like we do for tusb6010 dma. But of course it's possible
> that onenand has other issues too preventing the dma usage.

Hmm, that's probably what comment in omap3-n900.dts is saying:
"sys_ndmareq1 could be used by the driver, not as gpio65 though"
However board-rx51 (is that n900?) is using it as gpio pin.
Also omap2420-n8x0-common.dtsi comment says: "gpio-irq for dma: 26"
and it matches board-n8x0.c platform data configuration.
But I still missing pinmux configuration as we need to add it into
DT as well. I guess this was originally done in bootloader. Any hint
where can I get this info from?

Thanks,
	ladis